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→Routing information
[[File:VREF.png|thumb|center|600px]]
==== Other signals ====
The following table lists other signals that do not follow specific routing rules.
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Bora pin name'''
| align="center" style="background:#f0f0f0;"|'''Trace length<br>[mils]'''
|-
| IO_0_35||align="center"|1171,03
|-
| IO_L19N_T3_VREF_35||align="center"|2053,07
|-
| IO_L6N_T0_VREF_35||align="center"|2295,83
|-
|}
==== Related Xilinx documentation ====
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]
