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BoraXEVB

108 bytes added, 13:54, 1 March 2016
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Known limitations
| LCD_BKLT_PWM I/O voltage
| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.
|-
| FMC connector
| The FMC connector is the LPC version, not the HPC version listed in the specifications
|-
|}
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