Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→History2
==History2==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Version'''
| align="center" style="background:#f0f0f0;"|'''Date'''
| align="center" style="background:#f0f0f0;"|'''Notes'''
|-
| 1.0.0 || August 2015 ||
|-
|}
==Introduction==
Even if PL can share main SDRAM with PS, several applications need a dedicated bank for FPGA IPs in order to have exclusive access and to maximize bandwidth. In any case, since this additional SDRAM bank is accessible via AXI bus, it is mapped in the processor's memory space and thus it can be accessed by PS as well.
