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BELK-AN-003: Interfacing DDR3 SDRAM to PL

718 bytes added, 15:19, 31 August 2015
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|First release
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==History2==
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| align="center" style="background:#f0f0f0;"|'''Version'''
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| align="center" style="background:#f0f0f0;"|'''Date'''
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| align="center" style="background:#f0f0f0;"|'''Notes'''
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| 1.0.0 || August 2015 ||
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==Introduction==
The Vivado example project can be downloaded from the following URL:
[http://www.dave.eu/system/files/area-riservata/AN-BELK-003-bora-AXI-DDR3-BELK-2.1.0_no_results.xpr_.zip AN-BELK-003 Vivado project (without synthesis and implementation results)]
This project requires a 200 MHz clock source. It has been tested with
The bitstream and boot binaries can be downloaded from the following URL:
[http://www.dave.eu/system/files/area-riservata/AN-BELK-003.bitstream-boot-binaries.zip AN-BELK-003 binaries]
==SDRAM bank mapping==
The kernel patch can be downloaded from the following URL:
[http://www.dave.eu/system/files/area-riservata/AN-BELK-003_Add_AXI_DDR3.patch_.zip AN-BELK-003 Linux patch]
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