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BELK-AN-003: Interfacing DDR3 SDRAM to PL

74 bytes added, 10:06, 28 August 2015
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(1) For more information about this option, please contact technical support ([mailto:support-bora@dave.eusupport-bora@dave.eu]).
==Physical interfacing==
[[File:an-belk-003_02.png | 800px | AXI Memory Controller Block Design]]
The Vivado example project can be downloaded from the following URL:
At this URL '''TBD''' a Vivado example project is available. [] This project requires a 200 MHz clock source. It has been tested with
* Silicon Labs Si511BBA200M000BAG active ocillator populating reference XO1 on BoraEVB
* Micron MT41K64M16JT-15E DDR3 chip running at 400 MHz.
Here '''TBD''' The bitstream and boot binaries can be downloaded from the resulting bitstream.following URL: []
==SDRAM bank mapping==
</pre>
Here '''TBD''' The kernel patch can be downloaded from the kernel patch.following URL: []
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