Changes

BORA Evaluation Kit BELK is a development/test board designed to start working with the BORA Xpress platform and experimenting with the implemented features. The carrier board hosts an BORA Xpress CPU module and offers the following features: * 10/100/1000 Ethernet #0 (PS)* 10/100/1000 Ethernet #1 (Routed through EMIO)* 1x USB 2.0 OTG (MicroAB connector)* 1x Serial port (RS232 DB9)* 1x MicroSD* External DDR3 SDRAM bank** This memory bank is connected to bank 35 - powered @ 1.5V - that is optimized at PCB level to interface such devices.** This bank is expressly available for peripherals and/or IPs implemented in FPGA fabric. This solution '''permits these blocks to work without impacting on Bora's DDR3 memory bandwidth'''. To access this bank, MIG (Memory Interface Generator) controller has to be implemented on PL.*** MIG controller requires an external 200 MHz clock source.* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA* XADC** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of DDR3 memory.* JTAG port* Trace port* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]* Digilent Pmod™ Compatible expansion connectors* Headers for external for NAND flash and SPI NOR flash* 2.54mm-pitch pin-strip connectors for Bora PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)* Jumpers for voltage selection of the PL banks* +12V power connector