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# PMIC transitions from OFF to ON state
# PMIC initiates power-up sequence needed by MX6 processor
# NVCC_AXEL_I/O_3.3V/1.8V signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). For additional information, please refer to the [[Note]] below.
# configurable I/O power rails (NVCC_CSI_EXT, NVCC_EIM_EXT, NVCC_SD3_EXT, NVCC_LCD_EXT) are powered by carrier board
# PMIC VGEN6 LDO is turned on (this is the last regulator turned on automatically by PMIC)
# CPU_PORn is released.
==== Note on NVCC_AXEL_I/O_3.3V/1.8V ====
NVCC_AXEL_I/O_3.3V/1.8V is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals. Depending on the kind of such loads, NVCC_AXEL_I/O_3.3V/1.8V might not be able to drive them properly. In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution. VDD_SOM denotes the power rails used to power Axel Ultra SoM.
[[File:Axel-power-good.png]]
=== Power rails and related signals ===
