3,260
edits
Changes
m
→Pinout table
| 3||AM335X_I2C0_SCL||CPU.[I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]||C16||||||||Internally connected to a 10K pull-up resistor
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| 4||AM335X_GPMC_CS0n||CPU.[GPMC_CSN0///////GPIO1_29]||V6||||||||Internally connected to the NAND flash (if present)
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| 5||AM335X_I2C0_SDA||CPU.[I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5]||C17||||||||Internally connected to a 10K pull-up resistor
| 15||EEPROM_A1||||||||||||
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| 16||AM335X_GPMC_WEn||CPU.[GPMC_WEN//TIMER6/////GPIO2_4]||U6||||||||Internally connected to the NAND flash (if present)
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| 17||EEPROM_A0||||||||||||
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| 18||AM335X_GPMC_OEn_REn||CPU.[GPMC_OEN_REN//TIMER6/////GPIO2_4]||T7||||||||Internally connected to the NAND flash (if present)
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| 19||AM335X_EXT_WAKEUP||CPU.EXT_WAKEUP||C5||||||||
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| 20||AM335X_GPMC_ADVn_ALE||CPU.[GPMC_ADVN_ALE//TIMER4/////GPIO2_2]||R7||||||||Internally connected to the NAND flash (if present)
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| 21||DGND||||||||||||
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| 22||AM335X_GPMC_BE0n_CLE||CPU.[GPMC_BE0N_CLE//TIMER5/////GPIO2_5]||T6||||||||Internally connected to the NAND flash (if present)
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| 23||AM335X_RMII1_REFCLK||||H18||||||||HW option (not connected by default)
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| 24||AM335X_GPMC_BE1n||CPU.[GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28]||U18||||||||
| 25||AM335X_UART0_TXD||CPU.[UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11]||E16||||||||
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| 26||AM335X_GPMC_WAIT||CPU.[GPMC_WAIT0/GMII2_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_COL/UART4_RXD/GPIO0_30]||T17||||||||Internally connected to the NAND flash (if present)
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| 27||AM335X_UART0_RXD||CPU.[UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10]||E15||||||||
| 42||AM335X_GPMC_A6||CPU.[GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22]||U15||||||||
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| 43||AM335X_SPI0_SCLK||CPU.[SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2]||A17||||||||Internally connected to the NOR flash (if present)
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| 44||AM335X_GPMC_A7||CPU.[GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23]||T15||||||||
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| 45||AM335X_SPI0_D0||CPU.[SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3]||B17||||||||Internally connected to the NOR flash (if present)
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| 46||AM335X_GPMC_A8||CPU.[GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24]||V16||||||||
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| 47||AM335X_SPI0_D1||CPU.[SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4]||B16||||||||Internally connected to the NOR flash (if present)
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| 48||AM335X_GPMC_A9||CPU.[GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25]||U16||||||||
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| 49||AM335X_SPI0_CS0||CPU.[SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5]||A16||||||||Internally connected to the NOR flash (if present)
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| 50||AM335X_GPMC_A10||CPU.[GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26]||T16||||||||
| 55||USB0_ID||CPU.USB0_ID||P16||||||||
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| 56||AM335X_GPMC_AD0||CPU.[GPMC_AD0/MMC1_DAT0//////GPIO1_0]||U7||||||||Internally connected to the NAND flash (if present)
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| 57||USB0_DP||CPU.USB0_DP||N17||||||||
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| 58||AM335X_GPMC_AD1||CPU.[GPMC_AD1/MMC1_DAT1//////GPIO1_1]||V7||||||||Internally connected to the NAND flash (if present)
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| 59||USB0_DM||CPU.USB0_DM||N18||||||||
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| 60||AM335X_GPMC_AD2||CPU.[GPMC_AD2/MMC1_DAT2//////GPIO1_2]||R8||||||||Internally connected to the NAND flash (if present)
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| 61||DGND||||||||||||
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| 62||AM335X_GPMC_AD3||CPU.[GPMC_AD3/MMC1_DAT3//////GPIO1_3]||T8||||||||Internally connected to the NAND flash (if present)
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| 63||USB0_DRVVBUS||CPU.USB0_DRVVBUS||F16||||||||
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| 64||AM335X_GPMC_AD4||CPU.[GPMC_AD4/MMC1_DAT4//////GPIO1_4]||U8||||||||Internally connected to the NAND flash (if present)
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| 65||VUSB_VBUS0||CPU.USB0_VBUS||P15||||||||
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| 66||AM335X_GPMC_AD5||CPU.[GPMC_AD5/MMC1_DAT5//////GPIO1_5]||V8||||||||Internally connected to the NAND flash (if present)
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| 67||AM335x_EXTINTn||CPU.NMIn||B18||||||||
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| 68||AM335X_GPMC_AD6||CPU.[GPMC_AD6/MMC1_DAT6//////GPIO1_6]||R9||||||||Internally connected to the NAND flash (if present)
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| 69||AM335X_XDMA_EVENT_INTR0||CPU.[XDMA_EVENT_INTR0//TIMER4/CLKOUT1/SPI1_CS1/PR1_PRU1_PRU_R31_16/EMU2/GPIO0_19]||A15||||||||
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| 70||AM335X_GPMC_AD7||CPU.[GPMC_AD7/MMC1_DAT7//////GPIO1_7]||T9||||||||Internally connected to the NAND flash (if present)
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| 71||AM335X_XDMA_EVENT_INTR1||CPU.[XDMA_EVENT_INTR1//TCLKIN/CLKOUT2/TIMER7/PR1_PRU0_PRU_R31_16/EMU3/GPIO0_20]||D14||||||||
| 158||NC/Monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
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| 159||AM335X_GMII1_TXD2||CPU.[GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17]||K15||||||||Internally connected to the WDT (if present) – HW option
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| 160||NC/Monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
| 164||NC/Monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
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| 165||AM335X_GMII1_MDIO_CLK||CPU.[MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1]||M18||||||||Internally connected to the ETH PHY
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| 166||NC/Monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
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| 167||AM335X_GMII1_MDIO_DATA||CPU.[MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0]||M17||||||||Internally connected to the ETH PHY
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| 168||NC/Monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
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| 169||AM335X_GMII1_COL||CPU.[GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0]||H16||||||||Internally used for DDR power management (if required) – HW option
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| 170||OUT_PORSTn_OUT||||||||||||See [[#Reset scheme and voltage monitoring]].
