Changes

Jump to: navigation, search

Programmable logic (Bora)

596 bytes added, 12:56, 2 April 2014
m
FPGA Bank 13 (Zynq 7020 only)
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
| IO_L11N_T1_SRCC_13 || J3.136 ||
|-
| IO_L11P_T1_SRCC_13 || J3.134 ||
|-
| IO_L12N_T1_MRCC_13 || J3.137 ||
|-
| IO_L12P_T1_MRCC_13 || J3.135 ||
|-
| IO_L13N_T2_MRCC_13 || J3.130 ||
|-
| IO_L13P_T2_MRCC_13 || J3.128 ||
|-
| IO_L14N_T2_SRCC_13 || J3.131 ||
|-
| IO_L14P_T2_SRCC_13 || J3.129 ||
|-
| IO_L15N_T2_DQS_13 || J3.124 ||
|-
| IO_L15P_T2_DQS_13 || J3.122 ||
|-
| IO_L16N_T2_13 || J3.125 ||
|-
| IO_L16P_T2_13 || J3.123 ||
|-
| IO_L17N_T2_13 || J3.118 ||
|-
| IO_L17P_T2_13 || J3.116 ||
|-
| IO_L18N_T2_13 || J3.119 ||
|-
| IO_L18P_T2_13 || J3.117 ||
|-
| IO_L19N_T3_VREF_13 || J3.113 ||
|-
| IO_L19P_T3_13 || J3.111 ||
|-
| IO_L20N_T3_13 || J3.112 ||
|-
| IO_L20P_T3_13 || J3.110 ||
|-
| IO_L21N_T3_DQS_13 || J3.107 || |-| IO_L21P_T3_DQS_13 || J3.105 || |-| IO_L22N_T3_13 ||J3.106 || |-| IO_L22P_T3_13 || J3.104 || |-| IO_L6N_T0_VREF_13 || J3.100 ||
|-
|}
Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_13_.28XC7Z020_only.29 | PL Bank 13 routing]].

Navigation menu