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== FPGA Bank 35 ==
The following table reports the available pins connected to bank 35:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
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On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_35 | PL Bank 35 routing]].
== FPGA Bank 13 (Zynq 7020 only) ==
The following table reports the available pins connected to bank 13:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
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Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_13_.28XC7Z020_only.29 | PL Bank 13 routing]].
