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→FPGA Bank 34
== FPGA Bank 34 ==
The following table reports the available pins connected to bank 34:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
| IO_0_34 || J2.69 ||
|-
| IO_25_34 || J2.67 ||
|-
| IO_L10N_T1_34 || J2.65 ||
|-
| IO_L10P_T1_34 || J2.63 ||
|-
| IO_L11N_T1_SRCC_34 || J2.59 ||
|-
| IO_L11P_T1_SRCC_34 || J2.57 ||
|-
| IO_L12N_T1_MRCC_34 || ||
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|}
Regarding power voltage, take into consideration that Bank 35 is fixed at 3.3V. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_34 | PL Bank 34 routing]].
