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Highlighted rows are related to signals that are used for particular functions into the SOM.
=== FPGA Bank 34 ===
The following table reports the available pins connected to bank 34:
Regarding power voltage, take into consideration that Bank 34 is fixed at 3.3V.
====Routing information====
Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.
About power voltage, take into consideration that Bank 34 is fixed at 3.3V.
=== FPGA Bank 35 ===
The following table reports the available pins connected to bank 35:
{| class="wikitable" border="1"
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_35 | PL Bank 35 routing]].
====Routing information====
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz.
Signals have been grouped in the following classes:
Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog
inputs.
===== FDDR_ADDR class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.
|}
===== FDDR_CK class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.
|}
===== FDDR_BYTE0 class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signals.
|}
===== FDDR_BYTE1 class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE1 class signals.
|}
===== Related Xilinx documentation =====
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ds176_7Series_MIS.pdf Xilinx Memory Interface Solutions Data Sheet]
=== FPGA Bank 13 (Zynq 7020 only) ===
N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, '''VDDIO_BANK13 pins must not be left open and must be connected anyway''', either to ground or to an external I/O voltage as described in [[Programmable_logic_(Bora)#Introduction | I/O banks table]].
Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_13_.28XC7Z020_only.29 | PL Bank 13 routing]].
====Routing information====
Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.
