DADA SOM/DADA Hardware/Power and Reset/JTAG

History
Issue Date	Notes
2025/08/04	First documentation release

JTAG

JTAG signals are routed to the J1 primary connector of the DADA PCB. These signals output at 3.3 V logic.

For standard operation, the JTAG cell remains in reset: this is ensured by an on SoM pull-down resistor on JTAG_TRSTn signal. To enable a JTAG interface, drive the JTAG_TRSTn signal high.

Pin	Pin type	UNICA pin name	Notes
J1.56	Always present	DGND	-
J1.52	Always present	JTAG_TCK	Input CMOS 3.3 V
J1.50	Always present	JTAG_TMS	Input CMOS 3.3 V
J1.54	Always present	JTAG_TDO	Ouput CMOS 3.3 V
J1.48	Always present	JTAG_TDI	Input CMOS 3.3 V
J1.46	Variable	JTAG_TRSTn	Input CMOS 3.3 V with 10K pull-down.

See the pinout section for more details.

For additional features such as boundary scan, please contact DAVE Embedded Systems' team sales@dave.eu.