Reset scheme (Naon)

From DAVE Developer's Wiki
Revision as of 12:55, 2 May 2012 by DevWikiAdmin (talk | contribs) (→‎MRST (J2.102))

Jump to: navigation, search
HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
Info Box
Naon am387x-dm814x.png Applies to Naon

Five different signals are provided by Naon SOM. FOllowing sections describes in more detail each one.

MRST (J2.102)[edit | edit source]

This pin is connected to HDRST signal (cold reset) of PMIC TPS659113. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.

PORSTn (J2.109)[edit | edit source]

RSTOUTn (J2.91)[edit | edit source]

CPU_RESETn (J2.15)[edit | edit source]

JTAG_TRSTn (J2.100)[edit | edit source]

HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
Retrieved from "https://wiki.dave.eu/index.php?title=Reset_scheme_(Naon)&oldid=136"