Reset scheme (Maya)
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Contents
Accessible reset signals[edit | edit source]
Six different reset signals are provided by Maya SOM. Following sections describe in more detail each one.
Please also refer to the following image showing a simplified diagram of reset signals orgnaization.
PMIC_RESET[edit | edit source]
This pin is connected to HDRST signal (cold reset) of PMIC TPS659113. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.
PORSTn[edit | edit source]
PORSTn is a bidirectional open-drain signal. It is connected to:
- PORn input (Power-on Reset) of DM8148 processor
- NRESPWRON2 output of PMIC.
Internal pullup is 10kOhm.
RSTOUTn[edit | edit source]
This ouput signal is asserted by DM8148 processor until it gets out of reset. It is usually used to reset external memories and peripherals conneteced to processor. It is connected to:
- RSTOUT_WD_OUTn pad of DM8148 processor
- 2k2 pull down resistor.
In case it is used to reset devices on carrier board, its driving capability has to be taken into account.
CPU_RESETn[edit | edit source]
This input signal acts as External Warm Reset. It is connected to processor's RESETn pad. Internal pullup is 2.2kOhm.
JTAG_TRSTn[edit | edit source]
This input signal acts as Emulation Warm Reset. It is connected to processor's TRSTn pad. Internal pulldown is 4.7kOhm
MRSTn[edit | edit source]
This signal is connected to volage supervisor's manual-reset input. It is typically used to connect a push button.
When pulled low, it forces a reset at supervisor level that, in turn, triggers a power-on reset sequence.
Voltage monitor[edit | edit source]
Voltage monitoring of 3.3V rail is performed by is Texas Instruments TPS3106. Reset threshold is set to 3.15V.
