Programmable logic (Bora)

Info Box Applies to Bora

Introduction

The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

FPGA Bank	I/O Voltage	Voltage Pins	Notes
Bank 35	User defined VIO=FPGA_VDDIO_BANK35 1.8 to 3.3V	J1.2 J1.66 J1.67 J1.68
Bank 34	Fixed VIO=3.3 V	-
Bank 13	User defined VIO=FPGA_VDDIO_BANK13 1.8 to 3.3V	J3.95 J3.96 J3.97 J3.98 J3.99	Bank 13 is available only with Zynq XC7Z020 part number

Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
• Tn indicates the memory byte group [0-3]
• ZZZ indicates a MRCC, SRCC or DQS pin
• ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
• # indicates the bank number.

Highlighted rows are related to signals that are used for particular functions into the SOM.