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Creating and building example Vivado project (BELK/BXELK)

8 bytes added, 13:15, 23 September 2021
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It is assumed that the Zynq development environment has been set up properly (see [[Build_system_(BELK)|this page]] for more details).
===Command line based procedure===
{{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>
Define the correct ones according the target SoM.<br>
:**The PS configurations are the same for Bora and BoraLite boards.
===GUI based procedure===
{{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>
Define the correct ones according the target SoM.<br>
{{notelist}}
=== Downloading the bitstream to the device ===
Once the bitstream is ready, U-Boot itself can be used to download it onto the device. There are other options, however. For more details, please refer to [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot#Introduction|this section]].
=== Helloworld from UART0 ===
Using the FPGA bitstream previously created, it is possible to use serial tty port on Linux. The serial port is mapped to <code>/dev/ttyPS1</code> (this is because <code>/dev/ttyPS0</code> is the console mapped to UART1).
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