!BELK /BXELK version

<section begin=BELK/>==Creating and building example Vivado project==Command BELK/BXELK provides an example Vivado project for BORA/BORAX/BORALITE boards. This project allows to:*generate the PS configuration files to be used with U-boot SPL build*generate the bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following pictures).  [[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]][[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORAX example project]][[File:Boralite-default-vivado-project.png|thumb|center|400px|Block diagram of BORALITE example project]] This article describes how two build this project. Two procedures are described, the former is command line based procedure==while the latter is GUI based. The project is stored is a git repository, as described [[BORA_SOM/BELK-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]]. It is assumed that the Zynq development environment has been set up properly as described (see [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system|herethis page]]for more details). ===Command line based procedure==={{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>Define the correct ones according the target SoM.<br>For Bora SoM use:*<code>export BASE_NAME=bora</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraX SoM use:*<code>export BASE_NAME=borax</code>*<code>export UBOOT_PS7_DIR=borax</code>}} 

*copy the <code><bora_repo>/boards/board_parts/zynq/BELK_2.2.0</code> directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/

*enter the git directory and launch the following command*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "gen_bitstream" parameters allows for automatic building of the FPGA bitstream.}}:

. /opt/Xilinx/Vivado/2014.4<Vivado_version>/settings64.sh1shvivado -mode tcl -source build_projectscripts/recreate_prj_${BASE_NAME}_BASE.tcl -notrace -tclargs "-bitstreamgen_bitstream"

*at At the end of the bitstream build process, the <code>build_projectbuild_prj_*</code> script allows to automatically export hardware and lauch SDK to build the FSBL.*once the Xilinx SDK The bitstream file is ready, perform the following operations from the GUI:**Click on ''File -now present in <code> New -<bora_repo> Application Project''**Select the Project Name: ''bora_FSBL''**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''**Apply the patch, right-clicking on ''bora_FSBL'' in Project Explorer and then by clicking on ''Team -> Apply Patch/vivado/${BASE_NAME}.runs/impl_1/${BASE_NAME}_wrapper.''**From ''Browse...'' open the file bit</code> and <code><bora_repo>/patchvivado/${BASE_NAME}.runs/impl_1/belk-sd-boot${BASE_NAME}_wrapper.patchbin</code>.**Click ''Next''By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.**Select ''Apply Copy the patch to the selected file, folder or project:'' <code>ps7_init_gpl.c</code> and select <code>mainps7_init_gpl.ch</code> from ''bora_FSBL source files into U-> src''**Click ''Next''**Check that the patch is correctly applied to the boot source code and click on ''Finish''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of directory using the following optionscommand example for Bora:**launch this command manually:<code>cp <prebora_repo>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdkbd/SDK${BASE_NAME}/SDK_Exportip/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR{BASE_NAME}_processing_system7_0_0/boraps7_init_gpl.sdk* <U-boot_src_dir>/SDKboard/SDK_Exportdave/bora_FSBLbora/Debug${UBOOT_PS7_DIR}/bora_FSBL.bin</precode>:**:configure the automatic binary generation on project build. In Project Explorer, rightFollow [[BORA_SOM/BELK-click on ''bora_FSBL'' project, select CL/Development/C++ Build Settings and add the command <code>armBuilding_U-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on PostBoot | U-boot build instructions]] to build steps*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot:**select the using new PS configurations. ''bora_FSBL project'' in ''Project Explorer''**click on ''Xilinx Tools -> Create Zynq Boot Image''*if the project is correctly configured, the tool builds automatically all Please note that the component listed in the form, so just add U-Boot to the list*otherwise, select Create new BIF file and set binary images released along with BELK/BXELK were already built upon the output path and in Boot image partitions add the following files:**<code>bora_FSBLps7_init_gpl.elfc</code>, which can be found in the project Debug directory. N.B. check that the <u>Partition Type for FSBL is bootloader</u>**and <code>bora_wrapperps7_init_gpl.bith</code>, which is the bitstream source files generated by the Vivado project (<u>Partition Type must be Datafile</u>)**<code>u-bootdescribed in this article'''.elf</code>As such, which it is the compiled not generally required to rebuild U-Boot with .elf extension (<u>Partition Type must be Datafile</u>):*in ''Output path'', select *The PS configurations are the path same for the <u>BOOT.bin</u> fileBora and BoraLite boards.

==Creating and building a Zynq project for BORA=GUI based procedure==={{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>Define the correct ones according the target SoM.<br>For Bora SoM use:*<code>export BORA_SOM=Bora</code>*<code>export BASE_NAME=bora</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>export BORA_SOM=BoraLite</code>*<code>export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora</BORAX using the Vivado GUIcode>For BoraX SoM use:*<code>export BORA_SOM=BoraX</code>*<code>export BASE_NAME=borax</code>*<code>export UBOOT_PS7_DIR=borax</code>}}  *start the Zynq development server and login into the system*assuming that a local repository has not been created, clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code> *copy the <code><bora_repo>/boards/board_parts</zynq/BELK_2.2.0 code> directory to <vivado_2014.4_install_dircode><vivado_install_dir>/data/boards/board_parts/zynq</ code> :<pre>

sudo cp -r boards/board_parts/zynqopt/Xilinx/Vivado/<Vivado_version>/data/BELK_2.2.0 </pre>*launch the Vivado Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014201x.4y/datasettings32.sh</boardscode>}}:<pre>. /board_partsopt/zynqXilinx/launch Vivado v2014/201x.4 and y/settings64.shvivado</pre>*from the start page click on ''Create New Project''*click ''Next''*select the directory build project, insert the name of the project Project Name ''<prj_name>'' and click ''Next''*select ''RTL Project'', enable ''Do not specify sources at this time '' and click ''Next''*on the ''Default Part '' form, click on the ''Boards '' button to filter the available boards. Select BELK 2.2.0 ''${BORA_SOM}'' and click ''Next''*check the summary page and click ''Finish''in *For the block design there are two possible ways:**Add the existing BD within the repo: ***select ''Add sources'' from the ''Flow Navigator''***click on ''Add or create design sources''***select Add Files and add <code><bora_repo>/bd/${BASE_NAME}/${BASE_NAME}.bd</code>***check that the Vivado GUI option ''Copy sources into project'' is disabled and click finish**Create a new block design:***click on ''Create Block Design '' from the ''Flow Navigator''***insert bora ''${BASE_NAME}'' as ''Design name '' and click ''OK''***this creates a new block design. From the Diagram tab, add a new IP:****click the ''Add IP '' side button, or****click ''Add IP '' on the upper suggestions bar***double click on ''ZYNQ7 Processing System''***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation '' from the upper suggestions bar***check that ''Apply Board Preset '' is selected and click ''OK''****this applies the default settings for BORA /BORAX and creates the I/O ports for the DDR and MIO pins ***UART_0 and for CAN_0 connections must be manually created:****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 interfacesrespectively, otherwise correct manually***manually connect the <code>FCLK_CLK0 </code> signal to <code>M_AXI_GP0_ACLK </code> and save the block design***from the sources tab, select the BORA block design (bora<code>${BASE_NAME}.bd) </code> as ''Design Sources '' and from the context menu select ''Create HDL Wrapper''***on the next window, select Copy generated ''Let Vivado menage wrapper to allow user edits and auto-update'' and click ''OK''***this creates the Verilog bora_wrapperfile <code>${BASE_NAME}_wrapper.v file</code>. If this file is not automatically included in the project, add it using the ''Add sources '' option****select Add or create design sources and click ''Next''****select the bora_wrapper<code>>${BASE_NAME}_wrapper.v </code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/bora${BASE_NAME}/hdl/ </code> directory *select ''Add sources '' and click on ''Add or create constraints''*select the bora_pinout<code>${BASE_NAME}_pinout.xdc </code> and bora_timings<code>${BASE_NAME}_timings.xdc </code> files from the <code>constr </code> directory of the BORA repository*check that the option ''Copy constraints '' ''files into project '' is enableddisabled and click finish*create the synthesis, implementation and bitstream clicking ''Generate Bitstream '' from the ''Flow Navigator '' and wait the completion of the operation*once completed, select ''Open Implemented Design''*create the binary bitstream running the tcl script provided with the BORA repository. Launch ''Tools -> Run Tcl Script''*select the <code>generate_binary_bitstream.tcl </code> file from the <code>scripts </code> directory from the BORA repositoryselect File *The bitstream file is now present in <code><project_directory>/<prj_name>.runs/impl_1/${BASE_NAME}_wrapper.bit</code> and <code><project_directory>/<prj_name>.runs/impl_1/${BASE_NAME}_wrapper.bin</code>.*Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora::<code>cp <project_directory>/<prj_name>.srcs/sources_1/bd/${BASE_NAME}/ip/<prj_name>_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir> Export /board/dave/bora/${UBOOT_PS7_DIR}/</code>Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> Export Hardwareon source files generated by the next windowVivado project described in this article'''. As such, enable Include Bitstream and click OKit is not generally required to rebuild U-Boot.-----{{notelist}} now launch === Downloading the SDK session bitstream to generate the FSBL, clicking on File -> Launch SDKdevice ===once Once the Xilinx SDK bitstream is ready, perform U-Boot itself can be used to download it onto the following operations device. There are other options, however. For more details, please refer to [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot#Introduction|this section]]. === Helloworld from UART0 ===Using the GUI:Click FPGA bitstream previously created, it is possible to use serial tty port on File -Linux. The serial port is mapped to <code>/dev/ttyPS1</code> (this is because <code> New -/dev/ttyPS0</code> Application ProjectSelect is the Project Name: bora_FSBLconsole mapped to UART1).Click NextSelect TemplateHere below an example on C code for initializing and using UART0 through FPGA: Zynq FSBLClick on FinishApply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -<pre> Apply Patch#include <stdio.h>#include <stdlib.h>From Browse#include <string.h>#include <errno.h>#include <fcntl. open the file h> #include <bora_repotermios.h>/patch/belk-sd-boot.patchClick NextSelect Apply the patch to the selected fileint set_interface_attribs (int fd, int speed, int parity){ struct termios tty; memset (&tty, 0, sizeof tty); if (tcgetattr (fd, folder or project: and select main.c &tty) != 0) { printf("error %d from bora_FSBL tcgetattr", errno); return -> src1; }Click NextCheck that the patch is correctly applied to the source code and click on Finish cfsetospeed (&tty, speed);the FSBL cfsetispeed (ELF file&tty, speed) is built automatically;create the binary from the FSBL ELF chosing one of the following options:manually launch the command: arm tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8; // 8-xilinx-eabi-objcopy -v -O binary $PROJ_DIRbit chars // disable IGNBRK for mismatched speed tests; otherwise receive break // as \000 chars tty.c_iflag &= ~IGNBRK; //boradisable break processing tty.sdkc_lflag = 0; /SDK/SDK_Exportno signaling chars, no echo, /bora_FSBL/Debugno canonical processing tty.c_oflag = 0; /bora_FSBL/ no remapping, no delays tty.elf $PROJ_DIRc_cc[VMIN] = 0; //boraread doesn't block tty.sdkc_cc[VTIME] = 5; /SDK/SDK_Export0.5 seconds read timeout  tty.c_iflag &= ~(IXON | IXOFF | IXANY); /bora_FSBL/Debugshut off xon/bora_FSBLxoff ctrl  tty.binc_cflag |= (CLOCAL | CREAD);// ignore modem controls, // enable readingconfigure the automatic binary generation on project build tty. In Project Explorer, right-click on “bora_FSBL” project and select Cc_cflag &= ~(PARENB | PARODD); //C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}shut off parity tty.elf ${ProjName}c_cflag |= parity; tty.bin on Post-build stepsc_cflag &= ~CSTOPB;create the BOOT tty.bin image c_cflag &= ~CRTSCTS;  if (tcsetattr (fd, TCSANOW, &tty) != 0) { printf(single file including FSBL"error %d from tcsetattr", errno); return -1; } return 0;}   int main(){ int fd; char *portname = "/dev/ttyPS1";  char msg[] = "Hello World from BELK (FPGA and U-boot for uSD bootPS0 UART)!\n\r";  fd = open(portname, O_RDWR | O_NOCTTY | O_SYNC); if (fd < 0) { printf("error %d opening %s:%s", errno, portname, strerror (errno));select the bora_FSBL project in Project Explorer exit(1); } printf(msg);click on Xilinx Tools -> Create Zynq Boot Imageif the project is correctly configured set_interface_attribs (fd, the tool builds automatically all the component listed in the formB115200, so just add U-Boot 0); // set speed to the list. 115,200 bps, 8n1 (no parity)otherwise write(fd, msg, select Create new BIF file strlen(msg));  exit(0);}  </pre> and set the output path and in Boot image partitions add the following filesthen compile it:bora_FSBL.elf, which can be found in the project Debug directory. N.B. check that the Partition Type for FSBL is bootloaderbora_wrapper<pre>dvdk@vagrant:~/bora/rfs/belk/home/root$ source ~/env.bit, which is the bitstream generated by the Vivado project (Partition Type must be Datafile)sh u-bootdvdk@vagrant:~/bora/rfs/belk/home/root$ $CC hello_UART0.elf, which is the compiled Uc -Boot with .elf extension (Partition Type must be Datafile)o hello_UART0</pre> in Output path, select The program executed print out the path for msg string on the BOOTserial console and on <code>/dev/ttyPS1</code> port.bin file<section end=BELK/>