Difference between revisions of "BoraEVB-Lite"
DevWikiAdmin (talk | contribs) m (→JP2) |
DevWikiAdmin (talk | contribs) m (→JP2) |
||
| Line 52: | Line 52: | ||
|1, 10, 11, 16 || DGND || Ground || | |1, 10, 11, 16 || DGND || Ground || | ||
|- | |- | ||
| − | |2 || | + | |2 || RSV || RSV || Reserved |
|- | |- | ||
| − | |3 || | + | |3 || IO_L2P_T0_34 || - || - |
|- | |- | ||
| − | |4 || | + | |4 || IO_L19N_T3_VREF_34 || - || - |
|- | |- | ||
| − | |5 || | + | |5 || IO_L2N_T0_34 || - || - |
|- | |- | ||
| − | |6 || | + | |6 || IO_L18P_T2_34 || - || - |
|- | |- | ||
| − | |7 || | + | |7 || IO_L22P_T3_34 || - || - |
|- | |- | ||
| − | |8 || | + | |8 || IO_L18N_T2_34 || - || - |
|- | |- | ||
| − | |9 || | + | |9 || IO_L22N_T3_34 || - || - |
|- | |- | ||
| − | |12 || | + | |12 || IO_L15P_T2_DQS_34 || - || - |
|- | |- | ||
| − | |13 || | + | |13 || IO_L8P_T1_34 || - || - |
|- | |- | ||
| − | |14 || | + | |14 || IO_L15N_T2_DQS_34 || - || - |
|- | |- | ||
| − | |15 || | + | |15 || IO_L8N_T1_34 || - || - |
|- | |- | ||
|} | |} | ||
Revision as of 13:37, 6 September 2013
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
Info Box
|
|
The information here provided are preliminary and subject to change. |
|
Contents
Introduction[edit | edit source]
BoraEVB-Lite is a carrier board designed to host Bora system-on-module.
Block Diagram[edit | edit source]
The following picture shows Bora-EVB-Lite's block diagram:
Features[edit | edit source]
- 10/100/1000 Ethernet
- 1x USB OTG
- Serial port (RS232)
- 1x MicroSD
- External DDR3 SDRAM bank
- +12V power connector
- JTAG
- 2.54mm-pitch pin-strip connectors for Bora PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)
Known limitations[edit | edit source]
Board version CS040713 has the following limitations:
- USB OTG is not available
- MicroSD is not available
- DDR3 bank is not available
Connectors pinout[edit | edit source]
Pin strip connectors[edit | edit source]
JP2[edit | edit source]
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 10, 11, 16 | DGND | Ground | |
| 2 | RSV | RSV | Reserved |
| 3 | IO_L2P_T0_34 | - | - |
| 4 | IO_L19N_T3_VREF_34 | - | - |
| 5 | IO_L2N_T0_34 | - | - |
| 6 | IO_L18P_T2_34 | - | - |
| 7 | IO_L22P_T3_34 | - | - |
| 8 | IO_L18N_T2_34 | - | - |
| 9 | IO_L22N_T3_34 | - | - |
| 12 | IO_L15P_T2_DQS_34 | - | - |
| 13 | IO_L8P_T1_34 | - | - |
| 14 | IO_L15N_T2_DQS_34 | - | - |
| 15 | IO_L8N_T1_34 | - | - |
JP3[edit | edit source]
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | xxx | xxx | xxx |
| 2 | xxx | xxx | xxx |
| 3 | xxx | xxx | xxx |
| 4 | xxx | xxx | xxx |
| 5 | xxx | xxx | xxx |
| 6 | xxx | xxx | xxx |
| 7 | xxx | xxx | xxx |
| 8 | xxx | xxx | xxx |
| 9 | xxx | xxx | xxx |
| 10 | xxx | xxx | xxx |
| 11 | xxx | xxx | xxx |
| 12 | xxx | xxx | xxx |
| 13 | xxx | xxx | xxx |
| 14 | xxx | xxx | xxx |
| 15 | xxx | xxx | xxx |
| 16 | xxx | xxx | xxx |
JP4[edit | edit source]
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | xxx | xxx | xxx |
| 2 | xxx | xxx | xxx |
| 3 | xxx | xxx | xxx |
| 4 | xxx | xxx | xxx |
| 5 | xxx | xxx | xxx |
| 6 | xxx | xxx | xxx |
| 7 | xxx | xxx | xxx |
| 8 | xxx | xxx | xxx |
| 9 | xxx | xxx | xxx |
| 10 | xxx | xxx | xxx |
| 11 | xxx | xxx | xxx |
| 12 | xxx | xxx | xxx |
| 13 | xxx | xxx | xxx |
| 14 | xxx | xxx | xxx |
| 15 | xxx | xxx | xxx |
| 16 | xxx | xxx | xxx |
Schematics[edit | edit source]
- ORCAD: coming soon
- PDF: coming soon
BOM[edit | edit source]
- Coming soon
Layout[edit | edit source]
- Coming soon
Mechanical[edit | edit source]
- DXF: coming soon
- IDF (3D): coming soon
