BXELK-TN-002: Non-intrusive continuous multi-gigabit transceivers link monitoring

Info Box Applies to BORA Xpress

History

Version	Date	BELK version	Notes
0.9.0	September 2015	3.0.0	Internal draft

Introduction

This White Paper describes a practical application of the asymmetric multi-processing (AMP) configuration illustrated here. Specifically, this approach is used to implement a non-intrusive continuous link monitoring mechanism for the Xilinx Zynq multi-gigabit serial transceivers.

The starting point for this work is represented by the Xilinx Application Notes XAPP743 and XAPP1198, thus reading of these documents is highly recommended. The issue that this White Paper addresses is the need to monitor multi-gigabit transceivers link status when operating on the field in a non-intrusive way. Just imagine a product that is based on the architecture similar to the one depicted in the following figure. It is assumed that this architecture is quite representative of many real use cases.

Concept block diagram of the system without monitoring subsystem

A generic communication IP is implemented in Programmable Logic (PL) . This IP makes use of multi-gigabit transceivers to communicate with the peer at the other end of the physical link. On Processor Subsystem (PS) side, Linux operating system is used. On top of the kernel, several applications run, implementing high-level product's functionalities, including the management of sent and received data through the link shown in the figure. It is also assumed that the reliability of this link is a crucial factor for the successful product functioning. Thus a specific monitoring of its health has to be implemented in order to detect any deviation from normal working conditions that may affect link robustness such as:

• medium/long-term drift of the physical link characteristics
• significant part to part variations of such characteristics.

Last but not least, monitoring functionality has to be substantially non-intrusive with respect to:

• REQ1: software applications running in the Linux realm
• REQ2: user functions implemented in PL
• REQ3: transmission/reception of user data through the link
• REQ4: the overall system functionality.

Link monitoring

Before illustrating a possible solution, some further considerations about requirements listed in previous section are illustrated.

REQ1 through REQ4 specify in detail a generic requirement of non-intrusiveness. In other words, it is required that the implementation of link monitoring function is virtually transparent to the other parts of the system. As a consequence

• application software don't need any change when adding such functionality
• the cost of additional PL resources is neglectable with respect to the Microblaze-based approach described in
• physical link is not affected at all: normal operating, while monitoring is continuously in progress, is guaranteed by the integrated circuitry of GTP/GTX transceivers.

Block diagram of the solution here described is depicted in the following figure.

Concept block diagram of the system with monitoring subsystem

Conceptually, the system architecture amounts to the one illustrated in with two notable differences:

• since monitoring software is executed by the second Cortex A9 core, MicroBlaze infrastructure - that would consume PL resources - is not necessary
• thanks to the communication channel between the two ARM cores, core #0 can be signalled by core #1 in case an alert condition is detected at the transceivers level. Thus appropriate actions can be taken at application level.

This solution has been tested on BoraX/BoraXEVB platform implementing PCIe connectivity. PCIe Root Complex and AXI-to-DRP bridge have been integrated in PL. JTAG-to-AXI bridge has been included as well in order to keep the possibility to access monitoring data via JTAG during development/debugging stage. This allows retrieve data from host running Vivado and generate 2D statistical eye diagrams very easily (for more details please refer to ). The following figures show a couple of such diagrams.

PCIe Gen1 (2.5 Gbps) statistical eye diagram

PCIe Gen2 (5.0 Gbps) statistical eye diagram