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BoraEVB-Lite

8,433 bytes added, 12:28, 17 October 2018
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{{WorkInProgress}}{{InfoBoxTop}}{{Applies To Bora}}{{InfoBoxBottom}} {{WarningMessage|text=The information here This carrier board is '''obsolete''' and its shipment is discontinued. Starting from version 2.0.0 of the BELK, the official carrier board provided are preliminary and subject to changewith the BELK is the [[BoraEVB]].This wiki page remains published as reference, but won't be updated anymore}}
== Connectors pinout ==
 
=== Power supply - J7 ===
 
Power is provided through the J7 connector.
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || VIN || Power supply || Nominal: +12V
|-
|2 || DGND || Ground || -
|-
|}
 
=== UART0 - J17 ===
 
J17 is a standard DB9 connector for the RS232 two-wires UART0 port. The following table reports the connector's pinout:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1, 6, 4, 9
|N.C.
|N.C.
|Connected to protection diode array
|-
|2
|ZYNQ_UART1_RX
|Receive line
|
|-
|3
|ZYNQ_UART1_TX
|Transmit line
|
|-
|5
|DGND
|Ground
|
|-
|7, 8
|N.C.
|N.C.
|Connected to protection diode array
|-
|}
 
 
=== Ethernet port ETH0 - J8 ===
 
J8 is a RJ45 Gigabit Ethernet connector connected to the Bora integrated ethernet controller and PHY.
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || ETH_TXRX0_P || - || -
|-
|2 || ETH_TXRX0_M || - || -
|-
|3 || ETH_TXRX1_P || - || -
|-
|4 || ETH_TXRX2_P || - || -
|-
|5 || ETH_TXRX2_M || - || -
|-
|6 || ETH_TXRX1_M || - || -
|-
|7 || ETH_TXRX3_P || - || -
|-
|8 || ETH_TXRX3_M || - || -
|-
|9 || +3.3V || - || -
|-
|10 || ETH_SH || - || -
|-
|11, 13 || +3.3V || - || -
|-
|12 || 3.3V_ETH0_LED1 || - || -
|-
|14 || 3.3V_ETH0_LED2 || - || -
|-
|}
 
=== Pin strip connectors ===
==== JP2 ====
 
JP2 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|1, 10, 11, 16 || DGND || Ground || -
|-
|2 || IO_L19P_T3_34 ZYNQ_L19P_T3_34 || - || -Mount option
|-
|3 || IO_L2P_T0_34 || - || -
==== JP3 ====
 
JP3 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || PS_MIO28_501 || - || -
|-
|2, 10, 7, 15 || DGND || Ground || -
|-
|3 || PS_MIO29_501 || - || -
|-
|4 || PS_MIO34_501 || - || -
|-
|5 || PS_MIO30_501 || - || -
|-
|6 || PS_MIO35_501 || - || -
|-
|8 || PS_MIO36_501 || - || -
|-
|9 || PS_MIO31_501 || - || -
|-
|11 || PS_MIO32_501 || - || -
|-
|12 || PS_MIO37_501 || - || -
|-
|13 || PS_MIO33_501 || - || -
|-
|14 || PS_MIO38_501 || - || -
|-
|16 || PS_MIO39_501 || - || -
|-
|}
 
==== JP4 ====
 
JP4 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1, 10, 11, 16 || DGND || Ground || -
|-
|2 || IO_L9P_T1_DQS_34 || - || -
|-
|3 || IO_L21P_T3_DQS_34 || - || -
|-
|4 || IO_L9N_T1_DQS_34 || - || -
|-
|5 || IO_L21N_T3_DQS_34 || - || -
|-
|6 || IO_L7P_T1_34 || - || -
|-
|7 || IO_L20P_T3_34 || - || -
|-
|8 || IO_L7N_T1_34 || - || -
|-
|9 || IO_L20N_T3_34 || - || -
|-
|12 || ZYNQ_L6P_T0_34 || - || Mount option
|-
|13 || IO_L1P_T0_34 || - || -
|-
|14 || IO_L6N_T0_VREF_34 || - || -
|-
|15 || IO_L1N_T0_34 || - || -
|-
|}
 
==== JP5 ====
 
JP5 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1, 10, 11, 16 || DGND || Ground || -
|-
|2 || IO_L5P_T0_34 || - || -
|-
|3 || IO_L17P_T2_34 || - || -
|-
|4 || IO_L5N_T0_34 || - || -
|-
|5 || IO_L17N_T2_34 || - || -
|-
|6 || IO_L4P_T0_34 || - || -
|-
|7 || IO_L16P_T2_34 || - || -
|-
|8 || IO_L4N_T0_34 || - || -
|-
|9 || IO_L16N_T2_34 || - || -
|-
|12 || IO_L24P_T3_34 || - || -
|-
|13 || IO_L23P_T3_34 || - || -
|-
|14 || IO_L24N_T3_34 || - || -
|-
|15 || IO_L23N_T3_34 || - || -
|-
|}
 
 
==== JP6 ====
 
JP6 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1 , 10, 11, 16 || xxx DGND || xxx Ground || xxx-
|-
|2 || xxx IO_L16P_T2_13 || xxx - || xxx -
|-
|3 || xxx IO_L20P_T3_13 || xxx - || xxx-
|-
|4 || xxx IO_L16N_T2_13 || xxx - || xxx-
|-
|5 || xxx IO_L20N_T3_13 || xxx - || xxx-
|-
|6 || xxx IO_L22P_T3_13 || xxx - || xxx-
|-
|7 || xxx IO_L17P_T2_13 || xxx - || xxx-
|-
|8 || xxx IO_L22N_T3_13 || xxx - || xxx-
|-
|9 || xxx IO_L17N_T2_13 || xxx - || xxx-
|-
|10 12, 14 || xxx VDDIO_BANK13 || xxx - || xxx-
|-
|11 13 || xxx IO_L19P_T3_13 || xxx - || xxx-
|-
|12 15 || xxx IO_L19N_T3_VREF_13 || xxx - || xxx-
|-
|13 } ==== JP7 ==== JP7 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {|class="wikitable" | xxx || xxx || xxx-!Pin# !Pin name!Function!Notes
|-
|14 1, 6, 11, 12 || xxx DGND || xxx Ground || xxx-
|-
|15 2 || xxx IO_L14P_T2_SRCC_34 || xxx - || xxx-
|-
|3 || ZYNQ_L10P_T1_34 || - || Mount option|-|4 || IO_L14N_T2_SRCC_34 || - || -|-|5 || ZYNQ_L10N_T1_34 || - || Mount option|-|7 || ZYNQ_25_34 || - || Mount option|-|8 || IO_L11P_T1_SRCC_34 || - || -|-|9 || ZYNQ_0_34 || - || Mount option|-|10 || IO_L11N_T1_SRCC_34 || - || -|-|13 || IO_L3P_T0_DQS_PUDC_B_34 || - || -|-|14, 16 || xxx N.C. || Not connected || -|-|15 || IO_L3N_T0_DQS_34 || xxx - || xxx-
|-
|}
==== JP4 JP8 ==== JP8 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 7, 10, 13, 16 || DGND || Ground || -|-|2 || IO_L21P_T3_DQS_13 || - || - |-|3 || IO_L15P_T2_DQS_13 || - || -|-|4 || IO_L21N_T3_DQS_13 || - || -|-|5 || IO_L15N_T2_DQS_13 || - || -|-|6 || IO_L18P_T2_13 || - || -|-|8 || IO_L18N_T2_13 || - || -|-|9 || IO_L11P_T1_SRCC_13 || - || -|-|11 || IO_L11N_T1_SRCC_13 || - || -|-|12 || IO_L13P_T2_MRCC_13 || - || -|-|14 || IO_L13N_T2_MRCC_13 || - || -|-|15 || VDDIO_BANK13 || - || -|-|} ==== JP9 ==== JP9 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 7, 13 || DGND || Ground || -|-|2, 4, 6, 8, 10<br>12, 14, 15, 16 || N.C. || Not connected || - |-|3 || IO_L12P_T1_MRCC_34 || - || -|-|5 || IO_L12N_T1_MRCC_34 || - || -|-|9 || IO_L13P_T2_MRCC_34 || - || -|-|11 || IO_L13N_T2_MRCC_34 || - || -|-|} ==== JP10 ==== JP10 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 || IO_0_35 || - || -|-|2, 4 || VDDIO_BANK35 || - || - |-|3, 6, 9, 12, 15 || XADC_GND || - || -|-|5 || ZYNQ_AD14P_35 || - || Mount option|-|7 || ZYNQ_AD14N_35 || - || Mount option|-|8 || ZYNQ_T0_VREF_35 || - || Mount option|-|10 || ZYNQ_T3_VREF_35 || - || Mount option|-|11 || ZYNQ_AD1P_35 || - || Mount option|-|13 || ZYNQ_AD1N_35 || - || Mount option|-|14 || ZYNQ_AD3P_35 || - || Mount option|-|16 || ZYNQ_AD3N_35 || - || Mount option|-|} ==== JP11 ==== JP11 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 7 || XADC_AGND || Ground || -|-|2 || SYS_RSTn || - || - |-|3 || XADC_VN_R || - || -|-|4 || PORSTn || - || -|-|5 || XADC_VP_R || - || -|-|6 || MRSTn || - || -|-|8 || 1.0V_ENA || - || -|-|9 || FPGA_INIT_B || - || -|-|10, 15 || DGND || Ground || -|-|11 || FPGA_PROGRAM_B || - || -|-|12 || WD_SET0 || - || -|-|13 || FPGA_DONE || - || -|-|14 || WD_SET1 || - || -|-|16 || WD_SET2 || - || -|-|}  ==== JP13 ==== JP13 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 4, 9, 12 || DGND || Ground || -|-|2 || SPI0_CS0n || - || - |-|3 || ZYNQ_SPI0_SCLK/NAND_IO1 || - || -|-|5 || ZYNQ_SPI0_DQ0/NAND_ALE || - || -|-|6 || NAND_CS0/SPI0_CS1 || - || -|-|7 || ZYNQ_SPI0_DQ2/NAND_IO2 || - || -|-|8 || ZYNQ_SPI0_DQ1/NAND_WE || - || -|-|10 || ZYNQ_SPI0_DQ3/NAND_IO0 || - || -|-|11 || ZYNQ_NAND_RD_B || - || -|-|13 || ZYNQ_NAND_CLE || - || -|-|14 || NAND_BUSY || - || -|-|15 || NAND_IO4 || - || -|-|16 || NAND_IO3 || - || -|-|} ==== JP14 ==== JP14 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 || NAND_IO6 || - || -|-|2 || NAND_IO5 || - || - |-|3, 9 || DGND || Ground || -|-|4 || NAND_IO7 || - || -|-|5 || CLK125_NDO || - || -|-|6 || MEM_WPn || - || -|-|7 || ETH1_CLK125_NDO || - || -|-|8 || ETH_INTn || - || -|-|10 || ETH1_INTn || - || -|-|11 || INA_ALERT || - || -|-|12 || ETH1_RESETn || - || -|-|13 || RTC_INT/SQW || - || -|-|14 || IO_ETH0_RESETn || - || -|-|15 || PS_MIO15_500 || - || -|-|16 || IO_OTG_RESETn || - || -|-|} ==== JP15 ==== JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1 || xxx MON_VCCPLL || xxx - || xxx-
|-
|2 || xxx MON_3.3V || xxx - || xxx -
|-
|3 || xxx MON_XADC_VCC || xxx - || xxx-
|-
|4 || xxx MON_1V2_ETH || xxx - || xxx-
|-
|5 || xxx MON_FPGA_VDDIO_BANK35 || xxx - || xxx-
|-
|6 || xxx MON_VDDQ_1V5 || xxx - || xxx-
|-
|7 || xxx MON_FPGA_VDDIO_BANK34 || xxx - || xxx-
|-
|8 || xxx MON_1.8V || xxx - || xxx-
|-
|9 || xxx MON_FPGA_VDDIO_BANK13 || xxx - || xxx-
|-
|10 || xxx MON_1.0V || xxx - || xxx-
|-
|11 || xxx MON_1.8V_IO || xxx - || xxx-
|-
|12 || xxx DGND || xxx Ground || xxx-
|-
|13 } ==== JP16 ==== JP16 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {|| xxx || xxx || xxxclass="wikitable"
|-
|14 || xxx || xxx || xxx!Pin# !Pin name!Function!Notes
|-
|15 1 || xxx VDDIO_BANK13 || xxx - || xxx-
|-
|2, 4, 7, 13, 14 || xxx || - || - |-|3 || IO_L14P_T2_SRCC_13 || - || -|-|5 || IO_L14N_T2_SRCC_13 || - || -|-|6 || ZYNQ_L6N_T0_VREF_13 || - || -|-|8, 10, 12, 15, 16 || xxx DGND || Ground || -|-|9 || IO_L12P_T1_MRCC_13 || - || -|-|11 || IO_L12N_T1_MRCC_13 || xxx - || xxx-
|-
|}
==Schematics==
* ORCAD: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-lite-1.1.1-dsn.zip* PDF: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-lite_S.EVBB0000I0R_1.1.1_color.pdf
==BOM==
* Coming soon ==Layout==* Coming soon ==Mechanical==* DXFBoraEVB-Lite: coming soon* IDF (3D)https: coming soon//www.dave.eu/system/files/area-riservata/boraevb-lite_BOM_S%20EVBB0000I0R%201.1.1.CSV_.zip
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