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Furthermore, with some related control signals are avaible:
|-
|'''PMIC_ON_REQ'''
|PMIC Input
pulled-down with 100 kohm inside the SOM
|Externally or SoC
|PMIC
|PMIC starts power on sequence when PMIC_ON_REQ is asserted high.
Voltage monitors can trigger a power reset If a voltage drop occurs.
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== Reset scheme and control signals ==
The following picture shows the simplified block diagram of the reset scheme , power control signal and voltage monitoring.
[[File:AURA-reset-scheme.png | 800px]]
* '''PMIC_ON_REQ''', to start a PMIC power sequence, so that reboot the SoC
* '''CPU_PORn''', to force memories and peripherals to reset, in order to bring them in a known condition
* '''SOM_PGOOD''', to turn on circuitry external to the SOM
* '''PMIC_INTn''', to manage PMIC register interrupts
and provides these power control signals:
* '''PMIC_STBY_REQ''', to generate proper power for the SoC sleep mode
* '''ONOFF''', * '''PMIC_INTn''', to manage PMIC register interruptsturn off the SoC in a low-power use cases
The electrical and functional characteristics of these signals are listed in the following table:
|PMIC
|PMIC performs reset (cold or warm reset depends on its configuration register) when WDOG_B is asserted low.
|-
|'''PMIC_ON_REQ'''
|PMIC Input
pulled-down with 100 kohm inside the SOM
|Externally or SoC
|PMIC
|PMIC starts power on sequence when PMIC_ON_REQ is asserted high.
Voltage monitors can trigger a power reset If a voltage drop occurs.
This causes SoC reboot.
|-
|'''CPU_PORn'''
|SoC and External
|PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.
|-
|'''PMIC_STBY_REQ'''
|PMIC Input
pulled-down with 100 kohm inside the SOM
|Externally or SoC
|PMIC
|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high.
|Externally
|SoC
|SoC enters in power down when ONOFF is asserted highlow. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.
|}