!BELK /BXELK version

<section begin=BELK/>==IntroductionCreating and building example Vivado project==The following sections describe how BELK/BXELK provides an example Vivado project for BORA/BORAX/BORALITE boards. This project allows to perform :*generate the most common tasks for building PS configuration files to be used with U-boot SPL build*generate the software components for bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following pictures).  [[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA/example project]][[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORAXexample project]][[File:Boralite-default-vivado-project.png|thumb|center|400px|Block diagram of BORALITE example project]] This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based embedded system.  The project is stored is a git repository, as described [[BORA_SOM/BELK-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]]. It is assumed that the Zynq development environment has been set up properly as describe (see [[Build_system_(BORA_SOM/BELK)-L/Development/Build_system|herethis page]]for more details). ==Creating and building a Zynq project for BORA using =Command line based procedure==={{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>Define the correct ones according the command linetarget SoM.<br>For Bora SoM use:*<code>export BASE_NAME=bora</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraX SoM use:*<code>export BASE_NAME=borax</code>*<code>export UBOOT_PS7_DIR=borax</code>}}  

*copy the <code><bora_repo>/boards/board_parts/zynq/BELK_2.2.0</code> directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/

*enter the git directory and launch the following command*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "gen_bitstream" parameters allows for automatic building of the FPGA bitstream.}}:

. /opt/Xilinx/Vivado/2014.4<Vivado_version>/settings64.sh1shvivado -mode tcl -source build_projectscripts/recreate_prj_${BASE_NAME}_BASE.tcl -notrace -tclargs "-bitstreamgen_bitstream"

*at At the end of the bitstream build process, the <code>build_projectbuild_prj_*</code> script allows to automatically export hardware and lauch SDK .*The bitstream file is now present in <code><bora_repo>/vivado/${BASE_NAME}.runs/impl_1/${BASE_NAME}_wrapper.bit</code> and <code><bora_repo>/vivado/${BASE_NAME}.runs/impl_1/${BASE_NAME}_wrapper.bin</code>.*By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.**Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the FSBLfollowing command example for Bora::<code>cp <bora_repo>/bd/${BASE_NAME}/ip/${BASE_NAME}_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/${UBOOT_PS7_DIR}/</code>:*once Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Xilinx SDK Vivado project described in this article'''. As such, it is readynot generally required to rebuild U-Boot.:**The PS configurations are the same for Bora and BoraLite boards. ===GUI based procedure==={{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>Define the correct ones according the target SoM.<br>For Bora SoM use:*<code>export BORA_SOM=Bora</code>*<code>export BASE_NAME=bora</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraLite SoM use:*<code>export BORA_SOM=BoraLite</code>*<code>export BASE_NAME=boralite</code>*<code>export UBOOT_PS7_DIR=bora</code>For BoraX SoM use:*<code>export BORA_SOM=BoraX</code>*<code>export BASE_NAME=borax</code>*<code>export UBOOT_PS7_DIR=borax</code>}}  *start the Zynq development server and login into the system*assuming that a local repository has not been created, perform clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code> *copy the <code><bora_repo>/boards/</code> directory to <code><vivado_install_dir>/data/boards/</code> :<pre>cd <bora_repo>sudo cp -r boards/ /opt/Xilinx/Vivado/<Vivado_version>/data/</pre>*launch the Vivado Design Suite GUI with the following operations from commands{{efn|In a 32 bit system, Vivado settings are configured with the GUIfollowing command <code>/opt/Xilinx/Vivado/201x.y/settings32.sh</code>}}:<pre>. /opt/Xilinx/Vivado/201x.y/settings64.shvivado</pre>**Click from the start page click on ''File -> Create New -> Application Project''*click ''Next''*Select select the directory build project, insert the name of the Project Name: project ''<prj_name>'' and click ''bora_FSBLNext''**Click select ''RTL Project'', enable ''Do not specify sources at this time'' and click ''Next''**on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''Template: Zynq FSBL${BORA_SOM}'' and click ''Next''**Click on check the summary page and click ''Finish''*For the block design there are two possible ways:**Apply Add the existing BD within the patch, right-clicking on repo: ***select ''bora_FSBLAdd sources'' in Project Explorer and then by clicking on from the ''Team -> Apply Patch..Flow Navigator''**From *click on ''Browse...Add or create design sources'' open the file ***select Add Files and add <code><bora_repo>/patchbd/${BASE_NAME}/belk-sd-boot${BASE_NAME}.patchbd</code>**Click *check that the option ''Copy sources into project'' is disabled and click finish**Create a new block design:***click on ''Create Block Design'' from the ''NextFlow Navigator''**Select *insert ''${BASE_NAME}'' as ''Design name'' and click ''OK''Apply ***this creates a new block design. From the patch to Diagram tab, add a new IP:****click the selected file''Add IP'' side button, folder or project****click ''Add IP'' on the upper suggestions bar***double click on ''ZYNQ7 Processing System''***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar***check that ''Apply Board Preset'' is selected and click ''OK''****this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins***UART_0 and CAN_0 connections must be manually created:****right-clicking on each port (where mouse cursor switch to ''pencil'' ) and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually***manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design***from the sources tab, select the BORA block design <code>main${BASE_NAME}.cbd</code> as ''Design Sources'' and from the context menu select ''bora_FSBL -> srcCreate HDL Wrapper''**Click *on the next window, select ''NextLet Vivado menage wrapper and auto-update''**Check that the patch is correctly applied to the source code and click on ''FinishOK''***this creates the FSBL (ELF Verilog file <code>${BASE_NAME}_wrapper.v</code>. If this file) is built not automaticallyincluded in the project, add it using the ''Add sources'' option****select Add or create the binary from the FSBL ELF chosing one of the following options:design sources and click ''Next''**launch this command manually**select the <precode>>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora{BASE_NAME}_wrapper.sdkv</SDKcode> file from the <code><project_directory>/SDK_Export<prj_name>.srcs/bora_FSBLsources_1/Debugbd/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL{BASE_NAME}/Debughdl/bora_FSBL.bin</precode>directory **configure the automatic binary generation on project build. In Project Explorer, right-select ''Add sources'' and click on ''bora_FSBLAdd or create constraints'' project, *select C/C++ Build Settings and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjNameBASE_NAME}_pinout.elf xdc</code> and <code>${ProjNameBASE_NAME}_timings.binxdc</code> on Post-build steps*create files from the <code>BOOT.binconstr</code> image (single file including FSBL, FPGA directory of the BORA repository*check that the option ''Copy constraints'' ''files into project'' is disabled and U-boot for uSD boot:click finish**select create the synthesis, implementation and bitstream clicking ''bora_FSBL projectGenerate Bitstream'' in from the ''Project ExplorerFlow Navigator''and wait the completion of the operation**click on once completed, select ''Xilinx Tools -> Create Zynq Boot ImageOpen Implemented Design''*if create the project is correctly configured, binary bitstream running the tool builds automatically all tcl script provided with the component listed in the form, so just add UBORA repository. Launch ''Tools -Boot to the list> Run Tcl Script''*otherwise, select Create new BIF the <code>generate_binary_bitstream.tcl</code> file and set from the output path and in Boot image partitions add <code>scripts</code> directory from the following files:BORA repository**The bitstream file is now present in <code>bora_FSBL<project_directory>/<prj_name>.runs/impl_1/${BASE_NAME}_wrapper.elfbit</code>, which can be found in the project Debug directoryand <code><project_directory>/<prj_name>. Nruns/impl_1/${BASE_NAME}_wrapper.Bbin</code>. check that *Copy the <ucode>Partition Type for FSBL is bootloaderps7_init_gpl.c</ucode>**and <code>bora_wrapperps7_init_gpl.bith</code>, which is source files into U-boot source code directory using the bitstream generated by the Vivado project (following command example for Bora::<ucode>Partition Type must be Datafilecp <project_directory>/u<prj_name>)*.srcs/sources_1/bd/${BASE_NAME}/ip/<prj_name>_processing_system7_0_0/ps7_init_gpl.*<U-boot_src_dir>/board/dave/bora/${UBOOT_PS7_DIR}/</code>uFollow [[BORA_SOM/BELK-L/Development/Building_U-Boot | U-bootbuild instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.elfc</code>and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, which it is not generally required to rebuild U-Boot.-----{{notelist}} === Downloading the compiled bitstream to the device ===Once the bitstream is ready, U-Boot with itself can be used to download it onto the device. There are other options, however. For more details, please refer to [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot#Introduction|this section]]. === Helloworld from UART0 ===Using the FPGA bitstream previously created, it is possible to use serial tty port on Linux.elf extension The serial port is mapped to <code>/dev/ttyPS1</code> (this is because <ucode>Partition Type must be Datafile/dev/ttyPS0</ucode>is the console mapped to UART1). *in ''Output path'', select the path Here below an example on C code for the initializing and using UART0 through FPGA: <pre>#include <stdio.h>#include <stdlib.h>#include <string.h>#include <uerrno.h>BOOT#include <fcntl.binh> #include <termios.h> int set_interface_attribs (int fd, int speed, int parity){ struct termios tty; memset (&tty, 0, sizeof tty); if (tcgetattr (fd, &tty) != 0) { printf("error %d from tcgetattr", errno); return -1; }  cfsetospeed (&tty, speed); cfsetispeed (&tty, speed);  tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8; // 8-bit chars // disable IGNBRK for mismatched speed tests; otherwise receive break // as \000 chars tty.c_iflag &= ~IGNBRK; // disable break processing tty.c_lflag = 0; // no signaling chars, no echo, // no canonical processing tty.c_oflag = 0; // no remapping, no delays tty.c_cc[VMIN] = 0; // read doesn't block tty.c_cc[VTIME] = 5; // 0.5 seconds read timeout  tty.c_iflag &= ~(IXON | IXOFF | IXANY); // shut off xon/xoff ctrl  tty.c_cflag |= (CLOCAL | CREAD);// ignore modem controls, //u> fileenable reading tty.c_cflag &= ~(PARENB | PARODD); // shut off parity tty.c_cflag |= parity; tty.c_cflag &= ~CSTOPB; tty.c_cflag &= ~CRTSCTS;  if (tcsetattr (fd, TCSANOW, &tty) != 0) { printf("error %d from tcsetattr", errno); return -1; } return 0;}   int main(){ int fd; char *portname = "/dev/ttyPS1";  char msg[] ="Hello World from BELK (FPGA PS0 UART)!\n\r";  fd =Creating open(portname, O_RDWR | O_NOCTTY | O_SYNC); if (fd < 0) { printf("error %d opening %s: %s", errno, portname, strerror (errno)); exit(1); } printf(msg);  set_interface_attribs (fd, B115200, 0); // set speed to 115,200 bps, 8n1 (no parity) write(fd, msg, strlen(msg));  exit(0);}  </pre> and building a Zynq project for BORAthen compile it: <pre>dvdk@vagrant:~/bora/rfs/belk/home/root$ source ~/env.sh dvdk@vagrant:~/bora/rfs/belk/home/root$ $CC hello_UART0.c -o hello_UART0</BORAX using pre> The program executed print out the msg string on the Vivado GUI=serial console and on <code>/dev/ttyPS1</code> port.<section end=BELK/>