| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|14247|1.0.0}}

| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |32.0.0

| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |DESK 3.0.0 DESK release

From the Carrier <code>imx6ul-lynxaxelulite-som0013-cb002fcb003a.dts</code> device tree:<pre>&uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay";};......&iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_gpios>;

[ 1 imx6ul-axelulite {..163365] 2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 30, base_baud = 5000000) is a IMX [ 1.923126] 21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 65, base_baud = 5000000) is a IMX and from <code>imx6ul-lynx-som0013.dtsi</code><pre> pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; };  pinctrl_uart2: uart2grp uart { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 >; };  pinctrl_uart2_flow: uart2grp-flow { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 >; };  pinctrl_uart3: uart3grp { fsl,pins = < MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 >; };  pinctrl_uart3_flow: uart3grp-flow { fsl,pins = < MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 >; };   pinctrl_uart3_config: uart3grp-config { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x80000000 /* MPUART1_ON */ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 /* MPUART1_DEN */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 /* MPUART1_RXEN */ >; };... pinctrl_uart8: uart8grp { fsl,pins = < MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x1b0b1 MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x1b0b1 >; };  pinctrl_uart8_flow: uart8grp-1 { fsl,pins = < MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x1b0b1 MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x1b0b1 MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x80000000 MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x80000000 >; };  pinctrl_uart8_config: uart8grp-config { fsl,pins = < MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 /* MPUART0_DEN */ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 /* MPUART0_RXEN */ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x80000000 /* MPUART0_ON */ >; };...

[ 10.211906437613] 2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 3021, base_baud = 5000000) is a IMX[ 1.962230167221] 2024000.serial: ttymxc7 at MMIO 0x2024000 (irq = 31, base_baud = 5000000) is a IMXconsole [ 1.974074ttymxc0] 21e8000.serial: ttymxc1 at MMIO 0x21e8000 (irq = 65, base_baud = 5000000) is a IMXenabled[ 1.985128172839] 21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 6658, base_baud = 5000000) is a IMX

root@desk-mx6ul-lynxaxelulite:~# stty -F /dev/ttymxc7 ttymxc2 115200 -echo root@desk-mx6ul-lynxaxelulite:~# cat /dev/ttymxc7 ttymxc2 &

root@desk-mx6ul-lynxaxelulite:~# echo "Test loopback" > /dev/ttymxc7ttymxc2