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BELK-TN-012: Using XADC signal module

334 bytes added, 10:38, 26 January 2022
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!Notes
|-
|{{oldid|15689|1.0.0}}
|Dec 2021
|[[BELK/BXELK software components#BELK 4.1.0|4.1.0]]
|First release |-|1.1.0|Dec 2021|[[BELK/BXELK software components#BELK 4.1.0|4.1.0]]|Add "Electrical notes" section
|}
== Electrical notes ==
From an electrical perspective, in regard to the XADC module [[BORA SOM |BORA]], [[BORA Xpress SOM |BORA Xpress]], and [[BORA Lite SOM |BORA Lite]] SoMs implement the same scheme, which is depicted in the following image.
[[File:Zynq-7000-XADC-reference.png|center|thumb|519x519px]]
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the VREFP pad is internally connected to a 10ppm/°C 1.25V voltage reference .  For what concerns the input range, it is worth to remember that it is independent of the I/O voltage of bank 35 as illustrated in the Xilinx documentation: [[File:Zynq-7000-XADC-input-range.png|center|thumb|600x600px]]
== Pins usage==
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