Changes

Block diagram of the solution here described is depicted in the following figure.

[[File:Borax-wp001 02.png|thumb|center|400px|Concept block diagram of the system with monitoring subsystem]]

Conceptually, the system architecture amounts to the one illustrated in <ref name="XAPP743"></ref> with two notable differences:

*since monitoring software is executed by the second Cortex A9 core, MicroBlaze infrastructure - that would consume PL resources - is not necessary

This solution has been tested on BoraX/BoraXEVB platform implementing PCIe connectivity. PCIe Root Complex and AXI-to-DRP bridge have been integrated in PL. JTAG-to-AXI bridge has been included as well in order to keep the possibility to access monitoring data via JTAG during development/debugging stage. This allows to retrieve data from host running Vivado and generate 2D statistical eye diagrams very easily (for more details please refer to <ref name="XAPP743"></ref>). The following figures show a couple of such diagrams.

[[File:BORAx PCIe eyescan x1 gen1.jpg|thumb|center|400px|PCIe Gen1 (2.5 Gbps) statistical eye diagram]]

[[File:BORAx PCIe eyescan x1 gen2.jpg|thumb|center|400px|PCIe Gen2 (5.0 Gbps) statistical eye diagram]]