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→Power Supply Unit (PSU) and recommended power-up sequence
# Bora's PSU enables and sequences DC/DC regulators to turn circuitry on
# BOARD_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa).
Please note that '''FPGA Bank 13 and FPGA Bank 35 of the PL must be powered by carrier board even if they are not used to implement any function'''. Two dedicated power rails are available for this purpose (VDDIO_BANK35 and VDDIO_BANK13), '''offering the system designer the freedom to select the I/O voltage of these two banks'''. The power rails of both banks are enabled by the BOARD_PGOOD signal and are connected to the I/O power supply rail provided by the carrier board. Bank 13 and bank 35 are ''High Range'' (HR), hence the 1.2V - 3.3V voltage range is supported. For more details please refer to <ref name="DS187">Xilinx, ''DS187 Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics''</ref>.
Bora's PSU is designed to be robust against misbehaving power rails. However, the recommended power-on ramp for core and I/O supplies ranges from 1 to 6 V/ms.
