Bureaucrats, dave_user, Administrators
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Conceptually, the system architecture amounts to the one illustrated in <ref name="XAPP743"></ref> with two notable differences:
*since monitoring software is executed by the second Cortex A9 core, MicroBlaze infrastructure - that would consume PL resources - is not necessary
*thanks to the communication channel between the two ARM cores, core #0 can be signalled by core #1 in case an alert condition is detected at the transceivers level.Thus appropriate actions can be taken at application level. This solution has been tested on BoraX/BoraXEVB platform implementing PCIe connectivity. PCIe Root Complex and AXI-to-DRP bridge have been integrated in PL. JTAG-to-AXI bridge has been included as well in order to keep the possibility to access monitoring data via JTAG during development/debugging stage. This allows to retrieve data from host running Vivado and generate 2D statistical eye diagrams (for more details please refer to <ref name="XAPP743"></ref>). The following figures show a couple of such diagrams.[[File:BORAx PCIe eyescan x1 gen1.jpg|thumb|center|400px|PCIe Gen1 (2.5 Gbps) statistical eye diagram]][[File:BORAx PCIe eyescan x1 gen2.jpg|thumb|center|400px|PCIe Gen2 (5.0 Gbps) statistical eye diagram]]Even if not shown in the figure
==Conclusions==
