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Introduction
with Vivado IP Integrator and AXI4'', 19th November 2014''</ref>, thus reading of these documents is highly recommended.
The issue that this White Paper addresses is the need to monitor multi-gigabit transceivers link status in a <u>on the fieldnon-intrusive way</u> and in a <u>non-intrusive wayon the field</u>{{efn|That is after product has been sold and it is operating.}}. Just imagine a system product that is based on the architecture similar to the one depicted in the following figure, . It is assumed that it this architecture is assumed to be quite representative of many real use cases.
[[File:TBD.png|thumb|center|200px|Concept block diagram of the system]]
A generic communication IP is implemented In Programmable Logic (PL) a communication IP is implemented. This IP makes use of multi-gigabit transceivers to communicate with the peer at the other end of the physical link. On Processor Subsystem (PS) side, Linux operating system is used. On top of the kernel, several applications run, implementing high-level product's functionalities, including sending the management of data sent and receiving received data through the link shown in the figure. It is also assumed that the reliability of the this link is a crucial factor for the successful product functioning, thus . Thus a specific monitoring of its health has to be implemented in order to detect anomalies any deviation from normal working conditions that may affect link robustness such as:
*medium/long-term drift of the physical link characteristics
*significant part to part variations of such characteristics.
*<span id="REQ1">REQ1</span>: the software applications running in the Linux realm
*<span id="REQ2">REQ2</span>: the user functions implemented in PL
*<span id="REQ3">REQ3</span>: the overall system functionality.
==Proposed solution==
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