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# BOARD_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa).
Please note that FPGA Bank 13 and FPGA Bank 35 of the PL must be powered by carrier board even if they are not used to implement any function. Two dedicated power rails are available for this purpose (VDDIO_BANK35 and VDDIO_BANK13) and offers the system designer the freedom to select the I/O voltage of these two banks. The power rails of both banks are enabled by the BOARD_PGOOD signal and are connected to the I/O power supply rail provided by the carrier board.
Bora's PSU is designed to be robust against misbehaving power rails. However, the recommended power-on ramp for core and I/O supplies ranges from 1 to 6 V/ms.
'''N.B.''': Regarding power off, it is recommended taht I/O supply is turned off before core supply.
(1) This step is not mandatory and CB_PWR_GOOD can be left floating. CB_PWR_GOOD is provided to prevent, if necessary, Bora's PSU to turn on during ramp of carrier board 3.3VIN rail. Depending on carrier board's PSU design, this may lead to undesired glitches during ramp-up.
