3,260
edits
Changes
m
→Power Supply Unit (PSU) and recommended power-up sequence
# Bora's PSU enables and sequences DC/DC regulators to turn circuitry on
# BOARD_PGOOD is raised to indicate that Bora's internal power rails are stable and that carrier board's peripheral interfacing Zynq I/O can be turned on.
Please note that "bank FPGA Bank 13 and bank FPGA Bank 35 of Zynq the PL must be powered by carrier board even if they are not used to implement any function. Two dedicated power rails are available fot for this purpose (VDDIO_BANK35 and VDDIO_BANK13) and allow offers the system designer the freedom to select the I/O voltage of these two banks". These The power rails can be of both banks are enabled by the BOARD_PGOOD signal and are connected to main the I/O power supply rail (3.3VIN)provided by the carrier board.
(1) This step is not mandatory and CB_PWR_GOOD can be left floating. CB_PWR_GOOD is provided to prevent, if necessary, Bora's PSU to turn on during ramp of carrier board 3.3VIN rail. Depending on carrier board's PSU design, this may lead to undesired glitches during ramp-up.
