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==Connectors and Pinout Table==
This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors.
Each row in the pinout tables contains the following information:
* CPU.<x> : pin connected to CPU (processing system) pad named <x>
* FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
* CAN.<x> : pin connected to the CAN transceiver
* LAN.<x> : pin connected to the LAN PHY
* USB.<x> : pin connected to the USB transceiver
* NAND.<x>: pin connected to the flash NAND
* NOR.<x>: pin connected to the flash NOR
* SV.<x>: pin connected to voltage supervisor
* MTR: pin connected to voltage monitors
{| class="wikitable" style="width:50%;"
|-
| Connections to the BORA Xpress components
|-
|-
|'''Ball/pin #'''
| J1.87||ETH_MDIO||CPU.PS_MIO53_501||C11||Bank 501||I/O||1.8V||1kOhm pull-up
|-
| J1.89||ETH_MDC||CPU.PS_MIO51_501PS_MIO52_501||D13||Bank 501||I/O||1.8V||
|-
| J1.91||ETH_LED1||LAN.LED1/PME_N1||17||-||||1.8V||10kOhm pull-up