Power (AxelLite)

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Axel-lite 02.png Applies to Axel Lite

Power Supply Unit (PSU) and recommended power-up sequence

Implementing correct power-up sequence for i.MX6 processors is not a trivial task because several power rails are involved. Axel Lite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:

AxelLite-power-sequence.png

The PSU is composed of two main blocks:

  • power management integrated circuit (PMIC, Freescale PF0100E0 - on request this part is available in automotive grade)
  • additional generic power management circuitry that completes PMIC functionalities.

The PSU:

  • generates the proper power-up sequence required by i.MX processor and surrounding memories and peripherals
  • synchronizes the powering up of carrier board in order to prevent back power
  • provides some spare regulated voltages that can be used to power carrier board devices

Power-up sequence

The typical power-up sequence is the following:

  1. (optional) PMIC_LICELL is powered
  2. 3.3VIN main power supply rail is powered
  3. CPU_PORn (active-low) is driven low
  4. PMIC activates PMIC_VSNVS power output
  5. PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason)
  6. PMIC transitions from OFF to ON state
  7. PMIC initiates power-up sequence needed by MX6 processor
  8. BOARD_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). For additional information, please refer to the Note below.
  9. CPU_PORn is released.

Note on BOARD_PGOOD usage

BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals. Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly. In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution. VDD_SOM denotes the power rail used to power AXEL LITE SoM.

Axel-lite-power-good.png

Power rails and related signals

The following list describes in detail the power rails and the power related signals. Please note that PMIC regulators ouput voltages can be changed only if explicitly allowed.

  • 3.3VIN: this is external main power rail. Voltage range is 3.3V±5%
  • PMIC_CELL: PMIC's coin cell supply input/output
  • BOARD_PGOOD: this output signal is used to indicate when carrier board's circuitry interfacing Axel Lite's I/Os has to be powered up.

For further details, please refer to the PMIC documentation.