Pinout (Maya)

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Info Box
Maya 03.png Applies to Maya


Warning-icon.png The information here provided are preliminary and subject to change. Warning-icon.png

Introduction

This chapter contains the pinout description of 204-pin DDR3 SODIMM edge connector of Maya module.

Maya 04.jpg

Each row in the pinout table contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the Naon connectors
  • Internal connections: connections to the Naon components
    • CPU.<x> : pin connected to CPU pad named <x>
    • KEY.<x>: pin connected to the keypad controller
    • TSC.<x> : pin connected to the touchscreen controller
    • EEPROM.<x> : pin connected to the EEPROM
    • CAN.<x> : pin connected to the CAN transceiver
    • PMIC.<x> : pin connected to the Power Manager IC
    • LAN.<x> : pin connected to the LAN PHY
    • USB.<x> : pin connected to the USB transceiver
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • D = Differential
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
    • Voltage: I/O voltage levels

The Internal connection column reports the name of the microprocessor signal, which in turn contains references to all the peripheral functions that can be associated to that pin. For example, the following pin name CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/UART4_RXD/GP3[1] means that the pin can be used as:

  • VOUT[1]_B_CB_C[4]: Video output data, port 1, B/CB/C color bit 4
  • EMAC[1]_MRXD[0]: Ethernet MAC, port 1, [G]MII Receive Data, bit 0
  • VIN[1]A_D[1]: Video input channel 1, port A data input bit 1
  • UART[4]_RXD: UART port 4, receive data input
  • GP3[1]: General Purpose I/O port 3, channel 1

The following table reports all the function names that can be found on the Internal connection and the associated description.

Function name Description
VOUT[x] Digital video output. “x” represents the port number (0 or 1).
VIN[x]A/B Digital video input. “x” represents the capture number (0 or 1). Each capture has two ports (A and B)
EMAC[x] Ethernet MAC. “x” represents the port number (0 or 1)
UART[x] UART port. “x” represents the port number (0 to 5)
GPx[y] General Purpose I/O port. “x” represents the port number (0 to 3)
CAM Camera Interface
SPI[x] SPI channel. “x” represents the channel number (0 to 3)
DCAN[x] Controller Area Network module. “x” represents the module number (0 to 1)
HDMI High-Definition Multimedia Interface
SD[x] MMC/SD/SDIO interfaces. “x” represents the interface number (0 to 2)
GPMC General Purpose Memory Controller (local bus)
MD Management Data I/O module
MCA[x] Multi-Channel Audio Serial Port (McASP). “x” represents the port number (0 to 5)
I2C[x] I2C channel. “x” represents the channel number (0 to 3)
AUD Audio Reference Clock
TIMx General purpose timer. “x” represents the terminal number (0 to 7)

204-PIN SODIMM pinout

Pin Pin Name Internal connection(s)/Description Ball/pin # Supply Group Type Voltage Note
1 DGND Ground
2 DGND Ground
3 3.3V 3.3V power supply
4 3.3V 3.3V power supply
5 3.3V 3.3V power supply
6 3.3V 3.3V power supply
7 3.3V 3.3V power supply
8 3.3V 3.3V power supply
9 3.3V 3.3V power supply
10 3.3V 3.3V power supply
11 3.3V 3.3V power supply
12 3.3V 3.3V power supply
13 JTAG_TCK CPU.TCK W7 I 3.3V
14 DGND Ground
15 JTAG_RTCK CPU.RTCK AD4 O 3.3V
16 VBAT PMIC.VBACKUP D7 S
17 JTAG_TDI CPU.TDI Y7 I 3.3V
18 TV_OUT1 CPU.TV_OUT0 AH24 O
19 JTAG_TDO CPU.TDO AC5 O 3.3V
20 SD1_DAT0 CPU.SD1_DAT[0] P1 I/O 3.3V
21 JTAG_TMS CPU.TMS AA7 I/O 3.3V
22 SD1_DAT1 CPU.SD1_DAT[1]_SDIRQn P5 I/O 3.3V
23 JTAG_TRSTn CPU.TRSTn AA4 I 3.3V
24 SD1_DAT2 CPU.SD1_DAT[2]_SDRWn P4 I/O 3.3V
25 DGND Ground
26 SD1_DAT3 CPU.SD1_DAT[3] P6 I/O 3.3V
27 EMU1 CPU.EMU1 AE11 I/O 3.3V 4.7kOhm pull-up to 3.3V
28 DGND Ground
29 EMU0 CPU.EMU0 AG8 I/O 3.3V 4.7kOhm pull-up to 3.3V
30 SD1_CMD CPU.SD1_CMD/GP0[0] P2 I/O 3.3V
31 PMIC_RESET PMIC.HDRST L6 O 3.3V This signal is driven by internal reset circuitry.
32 SD1_CLK CPU.SD1_CLK P3 O 3.3V
33 MRSTn Active low, master reset input I 3.3V 10 kOhm pull-up to 3.3V.
34 SD1_DAT4 CPU.SD0_DAT[0]/SD1_DAT[4]/SC1_DATA/GP0[3] R7 I/O 3.3V
35 DGND Ground
36 SD1_DAT5 CPU.SD0_DAT[1]_SDIRQn/SD1_DAT[5]/SC1_CLK/GP0[4] Y5 I/O 3.3V
37 RSTOUTn CPU.RSTOUTn_WD_OUTn K6 O 3.3V 1 kOhm pull-down to ground
38 SD1_DAT6 CPU.SD0_DAT[2]_SDRWn/SD1_DAT[6]/SC1_RST/GP0[5] Y3 I/O 3.3V
39 PORSTn CPU.PORn, PMIC.NRESPWRON2 CPU.F1, PMIC.C7 I 3.3V 10 kOhm pull-up to 3.3V.
40 SD1_DAT7 CPU.SD0_DAT[3]/SD1_DAT[7]/SC1_VCCEN/GP0[6] Y4 I/O 3.3V
41 CPU_RESETn CPU.RESETn J5 I 3.3V
42 SD0_CMD CPU.SD0_CMD/SD1_CMD/GP0[2] N1 I/O 3.3V
43 CPU_NMIn CPU.NMIn H7 I 3.3V
44 SD0_CLK CPU.SD0_CLK/GP0[1] Y6 I/O 3.3V
45 EN_BCK2_LS PMIC.GPIO0; 3.3V I/O Power Rail Enable (active high) L4 O 3.3V SO-DIMM pin 45 is connected to PMIC GPIO0. The pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output (please see Pinout_(Maya)#EN_BCK2_LS_signal).
46 DGND Ground
47 N.C. This pin must be left unconnected.
48 VOUT0_B_CB_C2/GP2_22 CPU.VOUT[0]_B_CB_C[2]/EMU2/GP2[22] AG7 I/O 3.3V
49 SPI0_D1 CPU.SPI0_D1 AF3 I/O 3.3V
50 VOUT0_B_CB_C3/GP2_23 CPU.VOUT[0]_B_CB_C[3]/GP2[23] AE15 I/O 3.3V
51 SPI0_D0 CPU.SPI0_D0 AE3 I/O 3.3V
52 VOUT0_B_CB_C4 CPU.VOUT[0]_B_CB_C[4] AD11 O 3.3V
53 DGND Ground
54 VOUT0_B_CB_C5 CPU.VOUT[0]_B_CB_C[5] AD15 O 3.3V
55 SPI0_SCLK CPU.SPI0_SCLK AC7 3.3V
56 VOUT0_B_CB_C6 CPU.VOUT[0]_B_CB_C[6] AC10 O 3.3V
57 SPI0_SCS0n CPU.SPI0_SCS0n AD6 3.3V
58 VOUT0_B_CB_C7 CPU.VOUT[0]_B_CB_C[7] AB10 O 3.3V
59 SPI0_SCS1n/SD1_SDCD/SATA_ACT0_LED CPU.SPI[0]_SCS[1]n/SD1_SDCD/SATA_ACT0_LED/EDMA_EVT1/TIM4_IO/GP1[6] AE5 3.3V
60 VOUT0_B_CB_C8 CPU.VOUT[0]_B_CB_C[8] AF15 O 3.3V
61 VOUT0_CLK CPU.VOUT[0]_CLK AD12 O 3.3V
62 VOUT0_B_CB_C9 CPU.VOUT[0]_B_CB_C[9] AG15 O 3.3V
63 VOUT0_HSYNC CPU.VOUT[0]_HSYNC AC11 O 3.3V
64 DGND Ground
65 VOUT0_VSYNC CPU.VOUT[0]_VSYNC AB13 O 3.3V
66 VOUT0_G_Y_YC2/GP2_24 CPU.VOUT[0]_G_Y_YC[2]/EMU3/GP2[24] AH7 I/O 3.3V
67 VOUT0_AVID/VOUT0_FLD/GP2_21 CPU.VOUT[0]_AVID/VOUT[0]_FLD/SPI[3]_SCLK/TIM7_IO/GP2[21] AA10 O 3.3V
68 VOUT0_G_Y_YC3/GP2_25 CPU.VOUT[0]_G_Y_YC[3]GP2[25] AH15 I/O 3.3V
69 VOUT0_FLD/CAM_PCLK/GPMC_A12/GP2_02 CPU.VOUT[0]_FLD/CAM_PCLK/GPMC_A[12]/UART2_RTSn/GP2[02] AF18 I/O 3.3V
70 VOUT0_G_Y_YC4 CPU.VOUT[0]_G_Y_YC[4] AB8 O 3.3V
71 DGND Ground
72 VOUT0_G_Y_YC5 CPU.VOUT[0]_G_Y_YC[5] AB12 O 3.3V
73 VOUT0_R_CR2/GP2_26 CPU.VOUT[0]_R_CR[2]/EMU4/GP2[26] AD9 I/O 3.3V
74 VOUT0_G_Y_YC6 CPU.VOUT[0]_G_Y_YC[6] AA8 O 3.3V
75 VOUT0_R_CR3/GP2_27 CPU.VOUT[0]_R_CR[3]/GP2[27] AB9 I/O 3.3V
76 VOUT0_G_Y_YC7 CPU.VOUT[0]_G_Y_YC[7] AD14 O 3.3V
77 VOUT0_R_CR4 CPU.VOUT[0]_R_CR[4] AA9 O 3.3V
78 VOUT0_G_Y_YC8 CPU.VOUT[0]_G_Y_YC[8] AE14 O 3.3V
79 VOUT0_R_CR5 CPU.VOUT[0]_R_CR[5] AF8 O 3.3V
80 VOUT0_G_Y_YC9 CPU.VOUT[0]_G_Y_YC[9] AF14 O 3.3V
81 VOUT0_R_CR6 CPU.VOUT[0]_R_CR[6] AF6 O 3.3V
82 DGND Ground
83 VOUT0_R_CR7 CPU.VOUT[0]_R_CR[7] AF12 O 3.3V
84 USB0_DP CPU.USB0_DP AG11 D, I/O
85 VOUT0_R_CR8 CPU.VOUT[0]_R_CR[8] AE8 O 3.3V
86 USB0_DM CPU.USB0_DM AH11 D, I/O 3.3V
87 VOUT0_R_CR9 CPU.VOUT[0]_R_CR[9] AC13 O 3.3V
88 USB0_VBUS CPU.USB0_VBUSIN AG12 A, I
89 DGND Ground
90 USB1_VBUS CPU.USB1_VBUSIN AG14 A, I
91 USB0_DRVVBUS CPU.USB0_DRVVBUS/GP0[7] AF11 I/O
92 USB1_DP CPU.USB1_DP AG13 D, I/O
93 USB0_ID CPU.USB0_ID AG10 A, I
94 USB1_DM CPU.USB1_DM AH13 D, I/O
95 USB0_CE CPU.USB0_CE AH10
96 DGND Ground
97 USB1_DRVVBUS CPU.AUD_CLKIN0/MCA[0]_AXR[7]/MCA[0]_AHCLKX/MCA[3]_AHCLKX/ATL_CLKOUT1/ATL_CLKOUT0/VCX_VIC[0]/USB1_DRVVBUS L5 I/O
98 UART0_RXD CPU.UART0_RXD AH5 I 3.3V
99 USB1_ID CPU.USB1_ID AH12
100 UART0_TXD CPU.UART0_TXD AG5 O 3.3V
101 DEVOSC_WAKE/TIM5_IO/GP1_7 CPU.DEVOSC_WAKE/SPI[1]_SCS[1]n/TIM5_IO/GP1[7] J7 I/O 3.3V (1)
101 USB1_CE CPU.USB1_CE AH14 (1)
102 UART0_RTSn/DCAN1_RX CPU.UART0_RTSn/UART4_TXD/DCAN1_RX/SPI[1]_SCS[2]n/SD2_SDCD AF5 I/O 3.3V
103 DGND Ground
104 UART0_CTSn/DCAN1_TX CPU.UART0_RTSn/UART4_RXD/DCAN1_TX/SPI[1]_SCS[3]n/SD0_SDCD AE6 I/O 3.3V
105 GPMC_A11/CAM_FLD/CAM_WEn CPU.VOUT[1]_FLD/CAM_FLD/CAM_WEn/GPMC_A[11]/UART2_CTSn/GP0[28] AB23 I/O 3.3V
106 UART3_RTSn CPU.UART0_RIN/UART3_RTSn/UART1_RXD/GP1[5] AF4 I/O 3.3V
107 EMAC1_RGMII_RXCTL CPU.EMAC[0]_MRXD[3]/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/UART5_RXD J25 I/O 3.3V
108 UART3_RXD/SD1_POW CPU.UART0_DCDn/UART3_RXD/SPI[0]_SCS[3]n/I2C[2]_SCL/SD1_POW/GP1[2] AH4 I/O 3.3V
109 UART5_TXD CPU.EMAC[0]_MRXD[4]/GPMC_A[1]/UART5_TXD T23 I/O 3.3V
110 UART3_TXD/SD1_SDWP CPU.UART0_DSRn/UART3_TXD/SPI[0]_SCS[2]n/I2C[2]_SDA/SD1_SDWP/GP1[3] AG4 I/O 3.3V
111 CAN0_TX CPU.DCAN0_TX/UART2_TXD/I2C[3]_SDA/GP1[0] AH6 I/O 3.3V
112 UART3_CTSn CPU.UART0_DTRn/UART3_CTSn/UART1_TXD/GP1[4] AG2 I/O 3.3V
113 CAN0_RX CPU.DCAN0_RX/UART2_RXD/I2C[3]_SCL/GP1[1] 3.3V
114 DGND Ground
115 VIN0A_D0/GP1_11 CPU.VIN[0]A_D[0]/GP1[11] AF9 I/O 3.3V
116 MCA1_ACLKX CPU.MCA[1]_ACLKX U5 I/O 3.3V
117 VIN0A_D1/GP1_12 CPU.VIN[0]A_D[1]/GP1[12] AB11 I/O 3.3V
118 MCA1_AFSX CPU.MCA[1]_AFSX V3 3.3V
119 VIN0A_D2/GP2_7 CPU.VIN[0]A_D[2]/GP2[7] AC9 I/O 3.3V
120 MCA1_AXR0 CPU.MCA[1]_AXR[0]/SD0_DAT[4] V4 I/O 3.3V
121 DGND Ground
122 MCA1_AXR1 CPU.MCA[1]_AXR[1]/SD0_DAT[5] T6 I/O 3.3V
123 VIN0A_D3/GP2_8 CPU.VIN[0]A_D[3]/GP2[8] AE12 I/O 3.3V
124 TIM2_IO/GP0_8 CPU.AUD_CLKIN1/MCA[0]_AXR[8]/MCA[1]_AHCLKX/MCA[4]_AHCLKX/ATL_CLKOUT2/EDMA_EVT3/TIM2_IO/GP0[8] R5 I/O 3.3V
125 VIN0A_D4/GP2_9 CPU.VIN[0]A_D[4]/GP2[9] AH8 I/O 3.3V
126 MCA2_ACLKX/GP0_10 CPU.MCA[2]_ACLKX/GP0[10] U6 I/O 3.3V
127 VIN0A_D5/GP2_10 CPU.VIN[0]A_D[5]/GP2[10] AG16 I/O 3.3V
128 MCA2_AFSX/GP0_11 CPU.MCA[2]_AFSX/GP0[11] AA5 I/O 3.3V
129 VIN0A_D6/GP2_11 CPU.VIN[0]A_D[6]/GP2[11] AH16 I/O 3.3V
130 MCA2_AXR0/GP0_12 CPU.MCA[2]_AXR[0]/SD0_DAT[6]/UART5_RXD/GP0[12] N2 I/O 3.3V
131 VIN0A_D7/GP2_12 CPU.VIN[0]A_D[7]/GP2[12] AA11 I/O 3.3V
132 DGND Ground
133 VIN0A_D8_BD0/GP2_13 CPU.VIN[0]A_D[8]_BD[0]/GP2[13] AB15 I/O 3.3V
134 MCA2_AXR1/GP0_13 CPU.MCA[2]_AXR[1]/SD0_DAT[7]/UART5_TXD/GP0[13] V6 I/O 3.3V
135 VIN0A_D9_BD1/GP2_14 CPU.VIN[0]A_D[9]_BD[1]/GP2[14] AG9 I/O 3.3V
136 MCA2_AHCLKX/GP0_9 CPU.AUD_CLKIN2/MCA[0]_AXR[9]/MCA[2]_AHCLKX/MCA[5]_AHCLKX/ATL_CLKOUT3/EDMA_EVT2/TIM3_IO/GP0[9] H1 I/O 3.3V
137 VIN0A_D10_BD2/GP2_15 CPU.VIN[0]A_D[10]_BD[2]/GP2[15] AH9 I/O 3.3V
138 SPI3_SCS1n/GP3_14 CPU.VOUT[1]_R_CR[4]/EMAC[1]_MTXD[3]/VIN[1]A_D[15]/SPI[3]_SCS[1]n/GP3[14] AG27 I/O 3.3V
139 DGND Ground
140 SPI3_SCLK/GP3_15 CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/VIN[1]A_D[16]/PATA_D[8]/SPI[3]_SCLK/GP3[15] AC26 I/O 3.3V
141 VIN0A_D11_BD3/CAM_WEn CPU.VIN[0]A_D[11]_BD[3]/CAM_WEn/GP2[16] AH17 I/O 3.3V
142 SPI3_D1/GP3_16 CPU.VOUT[1]_R_CR[6]/EMAC[1]_MTXD[5]/VIN[1]A_D[17]/PATA_D[9]/SPI[3]_D[1]/GP3[16] AA25 I/O 3.3V
143 VIN0A_D12_BD4/GP2_17 CPU.VIN[0]A_D[12]_BD[4]/CLKOUT1/GP2[17] AG17 I/O 3.3V
144 SPI3_D0/GP3_17 CPU.VOUT[1]_R_CR[7]/EMAC[1]_MTXD[6]/VIN[1]A_D[18]/PATA_D[10]/SPI[3]_D[0]/GP3[17] V22 I 3.3V
145 VIN0A_D13_BD5/CAM_RESET CPU.VIN[0]A_D[13]_BD[5]/CAM_RESET/GP2[18] AF17 I/O 3.3V
146 VIN0A_FLD/UART5_RXD CPU.VIN[0]A_FLD/VIN[0]B_VSYNC/UART5_RXD/I2C[2]_SCL/GP2[1] AA20 I/O 3.3V
147 VIN0A_D14_BD6/CAM_STROBE CPU.VIN[0]A_D[14]_BD[6]/CAM_STROBE/GP2[19] AC12 I/O 3.3V
148 VIN0A_DE/UART5_TXD CPU.VIN[0]A_DE/VIN[0]B_HSYNC/UART5_TXD/I2C[2]_SDA/GP2[0] AE21 I/O 3.3V
149 VIN0A_D15_BD7/CAM_SHUTTER CPU.VIN[0]A_D[15]_BD[7]/CAM_SHUTTER/GP2[20] AC14 I/O 3.3V
150 DGND Ground
151 VIN0A_FLD/CAM_D5 CPU.VIN[0]A_FLD/CAM_D[5]/PATA_CS[0]n/GP0[20] AC22 I/O 3.3V
152 VIN[0]B_CLK/GP1_9 CPU.VIN[0]B_CLK/CLKOUT0/GP1[9] AE17 I/O 3.3V
153 VIN0A_DE/CAM_D7 CPU.VIN[0]A_DE/CAM_D[7]/GP0[18] AB17 I/O 3.3V 10kOhm pull-down
154 CAM_D4 CPU.VIN[0]B_FLD/CAM_D[4]/PATA_DIOWn/GP0[21] AD17 I/O 3.3V
155 VIN0A_CLK/GP2_2 CPU.VIN[0]A_CLK/GP2[2] AB20 I/O 3.3V
156 CAM_D6 CPU.VIN[0]B_DE/CAM_D[6]/GP0[19] AC15 I/O 3.3V
157 DGND Ground
158 GPMC_CS2n CPU.GPMC_CS[2]n/GPMC_A[24]/GP1[25] M25 I/O 3.3V
159 VIN0A_VSYNC/UART5_CTS CPU.VIN[0]A_VSYNC/UART5_CTSn/GP2[4] AD20 I/O 3.3V
160 GPMC_D0 CPU.GPMC_D[0]/BTMODE[0] U26 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
161 VIN0A_HSYNC/UART5_RTS CPU.VIN[0]A_HSYNC/UART5_RTSn/GP2[3] AC20 I/O 3.3V
162 GPMC_D1 CPU.GPMC_D[1]/BTMODE[1] Y28 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
163 GPMC_CS0n CPU.GPMC_CS[0]n/GP1[23] T28 I/O 3.3V
164 GPMC_D2 CPU.GPMC_D[2]/BTMODE[2] V27 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
165 HDMI_I2C_SCL CPU.I2C[1]_SCL/HDMI_SCL AF24 I/O 3.3V 10 kOhm pull-up to 3.3V.
166 GPMC_D3 CPU.GPMC_D[3]/BTMODE[3] W27 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
167 HDMI_I2C_SDA CPU.I2C[1]_SDA/HDMI_SDA AG24 I/O 3.3V 10 kOhm pull-up to 3.3V.
168 DGND Ground
169 I2C3_SCL CPU.VOUT[1]_B_CB_C[8]/EMAC[1]_MRXD[4]/VIN[1]A_D[5]/I2C[3]_SCL/GP3[5] AH26 I/O 3.3V 10 kOhm pull-up to 3.3V.
170 GPMC_D4 CPU.GPMC_D[4]/BTMODE[4] V26 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
171 I2C3_SDA CPU.VOUT[1]_B_CB_C[9]/EMAC[1]_MRXD[5]/VIN[1]A_D[6]/I2C[3]_SDA/GP3[6] AA24 I/O 3.3V 10 kOhm pull-up to 3.3V.
172 GPMC_D5 CPU.GPMC_D[5]/BTMODE[5] AA28 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
173 EMAC1_RGMII_TXD1 CPU.EMAC[0]_MTXD[1]/GPMC_A[8]/UART4_RXD H25 I/O 3.3V
174 GPMC_D6 CPU.GPMC_D[6]/BTMODE[6] U25 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
175 DGND Ground
176 GPMC_D7 CPU.GPMC_D[7]/BTMODE[7] V25 I/O 3.3V Signal is connected to CPU's pad through 22 Ohm resistor. On CPU side, this signal might be either pulled up to 3.3V through 1kOhm resistor or pulled down to ground through 10 kOhm resistor depending on default bootstrap configuration.
177 EMAC1_RGMII_TXCTL CPU.EMAC[0]_MTXD[2]/EMAC[1]_RMRXD[0]/GPMC_A[9]/UART4_TXD H22 I/O 3.3V
178 GPMC_WEn CPU.GPMC_WEn U28 O 3.3V
179 EMAC1_RGMII_TXD0 CPU.EMAC[0]_MTXD[3]/EMAC[1]_RMRXD[1]/GPMC_A[10]/UART4_CTSn H23 I/O 3.3V
180 GPMC_OEn_REn GPMC_OEn_REn T27 O 3.3V
181 EMAC1_RGMII_TXD2 CPU.EMAC[0]_MTXD[4]/EMAC[1]_RMRXER/GPMC_A[11]/UART4_RTSn G23 I/O 3.3V
182 GPMC_A0 CPU.VOUT1_B_CB_C[2]/GPMC_A[0]/VIN[1]A_D[7]/HDMI_CEC/SPI[2]_D[0]/GP3[30] AF28 I/O 3.3V
183 EMAC1_RGMII_RXD0 CPU.EMAC[0]_MTXD[6]/EMAC[1]_RMTXD[0]/GPMC_A[13]/UART1_TXD J22 I/O 3.3V
184 GPMC_A1/SD2_DAT3 CPU.SD2_DAT[3]/GPMC_A[1]/GP2[5] J28 I/O 3.3V
185 EMAC1_RGMII_TXD3 CPU.EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[1]/GPMC_A[14]/UART1_CTSn H24 I/O 3.3V
186 DGND Ground
187 EMAC1_RGMII_TXC CPU.EMAC[0]_MTXD[5]/EMAC[1]_RMCRSDV/GPMC_A[12]/UART1_RXD F27 I/O 3.3V
188 GPMC_A2/SD2_DAT2 CPU.SD2_DAT[2]_SDRWn/GPMC_A[2]/GP2[6] K27 I/O 3.3V
189 EMAC1_RGMII_RXD2 CPU.EMAC[0]_MTXEN/EMAC[1]_RMTXEN/GPMC_A[15]/UART1_RTSn J23 I/O 3.3V
190 GPMC_A3/SD2_DAT1 CPU.SD2_DAT[1]_SDIRQn/GPMC_A[3]/GP1[13] M24 I/O 3.3V
191 EMAC_REFCLK CPU.EMAC_RMREFCLK/TIM2_IO/GP1[10] J27 I/O 3.3V
192 MDIO_MDIO CPU.MDIO/GP1[12] P24 I/O 3.3V
193 DGND Ground
194 MDIO_MDCLK CPU.MDCLK/GP1[11] H28 I/O 3.3V
195 ETH_TX- Transmit negative line of differential pair (EMAC0 PHY) D
196 ETH_CTRD Magnetic's center tap (receive pair) A
197 ETH_TX+ Transmit positive line of differential pair (EMAC0 PHY) D
198 ETH_CTTD Magnetic's center tap (transmit pair) A
199 ETH_RX- Receive negative line of differential pair (EMAC0 PHY) D
200 EMAC0_PHY_LED_SPEED Speed LED indication (EMAC0 PHY) O
201 ETH_RX+ Receive positive line of differential pair (EMAC0 PHY) D
202 EMAC0_PHY_LED_LINK/ACT Link/activity LED indication (EMAC0 PHY) O
203 DGND Ground
204 DGND Ground

Additional notes

(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.

EN_BCK2_LS signal

This pin is a 5V push-pull signal connected to a voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as depicted below:

Maya EN BCK2 LS.jpg