Pinout (AxelLite)

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Axel-lite 02.png Applies to Axel Lite

Introduction

This chapter contains the pinout description of the Axel Lite module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM Axel Lite connector. Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the Axel Ultra connectors
  • Internal connections: connections to the Axel Ultra components
    • CPU.<x> : pin connected to CPU pad named <x>
    • CAN.<x> : pin connected to the CAN transceiver
    • PMIC.<x> : pin connected to the Power Manager IC
    • LAN.<x> : pin connected to the LAN PHY
    • NOR.<x>: pin connected to the flash NOR
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • D = Differential
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
  • Voltage: I/O voltage levels

J2 odd pins (1 to 203)

Pin Pin Name Internal Connections Ball/pin #
J2.1 DGND DGND
J2.3 3.3VIN INPUT VOLTAGE
J2.5 3.3VIN INPUT VOLTAGE
J2.7 3.3VIN INPUT VOLTAGE
J2.9 3.3VIN INPUT VOLTAGE
J2.11 DGND DGND
J2.13 ETH0_LED1 LAN.LED1/PME_N1 17
J2.15 ETH0_LED2 LAN.LED2 15
J2.17 DGND DGND
J2.19 ETH0_TXRX0_P LAN.TXRXP_A 2
J2.21 ETH0_TXRX0_M LAN.TXRXM_A 3
J2.23 ETH0_TXRX1_P LAN.TXRXP_B 5
J2.25 ETH0_TXRX1_M LAN.TXRXM_B 6
J2.27 ETH0_TXRX2_P LAN.TXRXP_C 7
J2.29 ETH0_TXRX2_M LAN.TXRXM_C 8
J2.31 ETH0_TXRX3_P LAN.TXRXP_D 10
J2.33 ETH0_TXRX3_M LAN.TXRXM_D 11
J2.35 DGND DGND
J2.37 SD3_RST CPU.SD3_RST D15
J2.39 SD3_DATA0 CPU.SD3_DATA0 E14
J2.41 SD3_DATA1 CPU.SD3_DATA1 F14
J2.43 SD3_DATA2 CPU.SD3_DATA2 A15
J2.45 SD3_DATA3 CPU.SD3_DATA3 B15
J2.47 SD3_DATA4 CPU.SD3_DATA4 D13
J2.49 SD3_DATA5 CPU.SD3_DATA5 C13
J2.51 SD3_DATA6 CPU.SD3_DATA6 E13
J2.53 SD3_DATA7 CPU.SD3_DATA7 F13
J2.55 SD3_CMD CPU.SD3_CMD B13
J2.57 DGND DGND
J2.59 SD3_CLK CPU.SD3_CLK D14
J2.61 SD2_DATA0 CPU.SD2_DATA0 A22
J2.63 SD2_DATA1 CPU.SD2_DATA1 E20
J2.65 SD2_DATA2 CPU.SD2_DATA2 A23
J2.67 SD2_DATA3 CPU.SD2_DATA3 B22
J2.69 SD2_CMD CPU.SD2_CMD F19
J2.71 SD2_CLK CPU.SD2_CLK C21
J2.73 DGND DGND
J2.75 SD1_DAT0 CPU.SD1_DAT0 A21
J2.77 SD1_DAT1 CPU.SD1_DAT1 C20
J2.79 SD1_DAT2 CPU.SD1_DAT2 E19
J2.81 SD1_DAT3 CPU.SD1_DAT3 F18
J2.83 SD1_CMD CPU.SD1_CMD B21
J2.85 SD1_CLK CPU.SD1_CLK D20
J2.87 DGND DGND
J2.89 KEY_COL0/ECSPI1_SCLK CPU.KEY_COL0 W5
J2.91 KEY_ROW0/ECSPI1_MOSI CPU.KEY_ROW0 V6
J2.93 KEY_COL1/ECSPI1_MISO CPU.KEY_COL1 U7
J2.95 KEY_ROW1/ECSPI1_SS0 CPU.KEY_ROW1 U6
J2.97 KEY_COL2/ECSPI1_SS1 CPU.KEY_COL2 W6
J2.99 KEY_ROW2 CPU.KEY_ROW2 W4
J2.101 KEY_COL3/I2C2_SCL CPU.KEY_COL3 U5
J2.103 KEY_ROW3/I2C2_SDA CPU.KEY_ROW3 T7
J2.105 KEY_COL4 CPU.KEY_COL4 T6
J2.107 KEY_ROW4 CPU.KEY_ROW4 V5
J2.109 DGND DGND
J2.111 HDMI_CLKN CPU.HDMI_CLKN J5
J2.113 HDMI_CLKP CPU.HDMI_CLKP J6
J2.115 HDMI_D0N CPU.HDMI_D0N K5
J2.117 HDMI_D0P CPU.HDMI_D0P K6
J2.119 HDMI_D1N CPU.HDMI_D1N J3
J2.121 HDMI_D1P CPU.HDMI_D1P J4
J2.123 HDMI_D2N CPU.HDMI_D2N K3
J2.125 HDMI_D2P CPU.HDMI_D2P K4
J2.127 HDMI_CEC_IN CPU.HDMI_DDCCEC K2
J2.129 HDMI_HPD CPU.HDMI_HPD K1
J2.131 DGND DGND
J2.133 LVDS0_CLK_N CPU.LVDS0_CLK_N V4
J2.135 LVDS0_CLK_P CPU.LVDS0_CLK_P V3
J2.137 LVDS0_TX0_N CPU.LVDS0_TX0_N U2
J2.139 LVDS0_TX0_P CPU.LVDS0_TX0_P U1
J2.141 LVDS0_TX1_N CPU.LVDS0_TX1_N U4
J2.143 LVDS0_TX1_P CPU.LVDS0_TX1_P U3
J2.145 LVDS0_TX2_N CPU.LVDS0_TX2_N V2
J2.147 LVDS0_TX2_P CPU.LVDS0_TX2_P V1
J2.149 LVDS0_TX3_N CPU.LVDS0_TX3_N W2
J2.151 LVDS0_TX3_P CPU.LVDS0_TX3_P W1
J2.153 DGND DGND
J2.155 LVDS1_CLK_N CPU.LVDS1_CLK_N Y3
J2.157 LVDS1_CLK_P CPU.LVDS1_CLK_P Y4
J2.159 LVDS1_TX0_N CPU.LVDS1_TX0_N Y1
J2.161 LVDS1_TX0_P CPU.LVDS1_TX0_P Y2
J2.163 LVDS1_TX1_N CPU.LVDS1_TX1_N AA2
J2.165 LVDS1_TX1_P CPU.LVDS1_TX1_P AA1
J2.167 LVDS1_TX2_N CPU.LVDS1_TX2_N AB1
J2.169 LVDS1_TX2_P CPU.LVDS1_TX2_P AB2
J2.171 LVDS1_TX3_N CPU.LVDS1_TX3_N AA3
J2.173 LVDS1_TX3_P CPU.LVDS1_TX3_P AA4
J2.175 DGND DGND
J2.177 EIM_D19 CPU.EIM_D19 G21
J2.179 EIM_D20 CPU.EIM_D20 G20
J2.181 EIM_D21 CPU.EIM_D21 H20
J2.183 EIM_D22 CPU.EIM_D22 E23
J2.185 EIM_D23 CPU.EIM_D23 D25
J2.187 EIM_D24 CPU.EIM_D24 F22
J2.189 EIM_D25 CPU.EIM_D25 G22
J2.191 EIM_D26 CPU.EIM_D26 E24
J2.193 EIM_D27 CPU.EIM_D27 E25
J2.195 EIM_D28 CPU.EIM_D28 G23
J2.197 EIM_D29 CPU.EIM_D29 J19
J2.199 EIM_D30 CPU.EIM_D30 J20
J2.201 EIM_D31 CPU.EIM_D31 H21
J2.203 DGND DGND

J2 even pins (2 to 204)

Pin Pin Name Internal Connections Ball/pin #
J2.2 DGND DGND
J2.4 3.3VIN INPUT VOLTAGE
J2.6 3.3VIN INPUT VOLTAGE
J2.8 3.3VIN INPUT VOLTAGE
J2.10 3.3VIN INPUT VOLTAGE
J2.12 DGND DGND
J2.14 PMIC_LICELL PMIC.LICELL 42
J2.16 CPU_ONOFF CPU.CPU_ONOFF D12
J2.18 BOARD_PGOOD
J2.20 BOOT_MODE_SEL BOOT MODE SELECTION
J2.22 CPU_PORN CPU.CPU_PORN C11
J2.24 PMIC_PWRON PMIC.PWRON 56
J2.26 GPIO_0 CPU.GPIO_0 T5
J2.28 GPIO_1 CPU.GPIO_1 T4
J2.30 DGND DGND
J2.32 GPIO_2 CPU.GPIO_2 T1
J2.34 GPIO_3/I2C3_SCL CPU.GPIO_3 R7
J2.36 GPIO_4 CPU.GPIO_4 R6
J2.38 GPIO_5 CPU.GPIO_5 R4
J2.40 GPIO_6/I2C3_SDA CPU.GPIO_6 T3
J2.42 GPIO_7//FLEXCAN1_H CPU.GPIO_7 R3
J2.44 GPIO_8//FLEXCAN1_L CPU.GPIO_8 R5
J2.46 GPIO_9 CPU.GPIO_9 T2
J2.48 GPIO_16 CPU.GPIO_16 R2
J2.50 GPIO_17 CPU.GPIO_17 R1
J2.52 GPIO_18 CPU.GPIO_18 P6
J2.54 GPIO_19 CPU.GPIO_19 P5
J2.56 DGND DGND
J2.58 CSI0_PIXCLK CPU.CSI0_PIXCLK P1
J2.60 CSI0_MCLK CPU.CSI0_MCLK P4
J2.62 CSI0_VSYNC CPU.CSI0_VSYNC N2
J2.64 CSI0_DATA_EN CPU.CSI0_DATA_EN P3
J2.66 CSI0_DAT4 CPU.CSI0_DAT4 N1
J2.68 CSI0_DAT5 CPU.CSI0_DAT5 P2
J2.70 CSI0_DAT6 CPU.CSI0_DAT6 N4
J2.72 CSI0_DAT7 CPU.CSI0_DAT7 N3
J2.74 CSI0_DAT8 CPU.CSI0_DAT8 N6
J2.76 CSI0_DAT9 CPU.CSI0_DAT9 N5
J2.78 CSI0_DAT10 CPU.CSI0_DAT10 M1
J2.80 CSI0_DAT11 CPU.CSI0_DAT11 M3
J2.82 DGND DGND
J2.84 CLK1_N CPU.CLK1_N C7
J2.86 CLK1_P CPU.CLK1_P D7
J2.88 CLK2_N CPU.CLK2_N C5
J2.90 CLK2_P CPU.CLK2_P D5
J2.92 PCIE_RXN CPU.PCIE_RXN B1
J2.94 PCIE_RXP CPU.PCIE_RXP B2
J2.96 PCIE_TXN CPU.PCIE_TXN A3
J2.98 PCIE_TXP CPU.PCIE_TXP B3
J2.100 DGND DGND
J2.102 CSI_CLK0M CPU.CSI_CLK0M F4
J2.104 CSI_CLK0P CPU.CSI_CLK0P F3
J2.106 CSI_D0M CPU.CSI_D0M E4
J2.108 CSI_D0P CPU.CSI_D0P E3
J2.110 CSI_D1M CPU.CSI_D1M D1
J2.112 CSI_D1P CPU.CSI_D1P D2
J2.114 CSI_D2M CPU.CSI_D2M E1
J2.116 CSI_D2P CPU.CSI_D2P E2
J2.118 CSI_D3M CPU.CSI_D3M F2
J2.120 CSI_D3P CPU.CSI_D3P F1
J2.122 DGND DGND
J2.124 DI0_PIN15 CPU.DI0_PIN15 N21
J2.126 DI0_PIN4 CPU.DI0_PIN4 P25
J2.128 DI0_PIN3 CPU.DI0_PIN3 N20
J2.130 DI0_PIN2 CPU.DI0_PIN2 N25
J2.132 DI0_DISP_CLK CPU.DI0_DISP_CLK N19
J2.134 DISP0_DAT0 CPU.DISP0_DAT0 P24
J2.136 DISP0_DAT1 CPU.DISP0_DAT1 P22
J2.138 DISP0_DAT2 CPU.DISP0_DAT2 P23
J2.140 DISP0_DAT3 CPU.DISP0_DAT3 P21
J2.142 DISP0_DAT4 CPU.DISP0_DAT4 P20
J2.144 DISP0_DAT5 CPU.DISP0_DAT5 R25
J2.146 DGND DGND
J2.148 DISP0_DAT6 CPU.DISP0_DAT6 R23
J2.150 DISP0_DAT7 CPU.DISP0_DAT7 R24
J2.152 DISP0_DAT8 CPU.DISP0_DAT8 R22
J2.154 DISP0_DAT9 CPU.DISP0_DAT9 T25
J2.156 DISP0_DAT10 CPU.DISP0_DAT10 R21
J2.158 DISP0_DAT11 CPU.DISP0_DAT11 T23
J2.160 DISP0_DAT12 CPU.DISP0_DAT12 T24
J2.162 DISP0_DAT13 CPU.DISP0_DAT13 R20
J2.164 DGND DGND
J2.166 DISP0_DAT14 CPU.DISP0_DAT14 U25
J2.168 DISP0_DAT15 CPU.DISP0_DAT15 T22
J2.170 DISP0_DAT16 CPU.DISP0_DAT16 T21
J2.172 DISP0_DAT17 CPU.DISP0_DAT17 U24
J2.174 DISP0_DAT18 CPU.DISP0_DAT18 V25
J2.176 DISP0_DAT19 CPU.DISP0_DAT19 U23
J2.178 DISP0_DAT20 CPU.DISP0_DAT20 U22
J2.180 DISP0_DAT21 CPU.DISP0_DAT21 T20
J2.182 DISP0_DAT22 CPU.DISP0_DAT22 V24
J2.184 DISP0_DAT23 CPU.DISP0_DAT23 W24
J2.186 USB_OTG_VBUS CPU.USB_OTG_VBUS E9
J2.188 USB_H1_VBUS CPU.USB_H1_VBUS D10
J2.190 DGND DGND
J2.192 ENET_RX_ER (*) CPU.ENET_RX_ER W23
J2.194 ENET_RXD0 (*) CPU.ENET_RXD0 W21
J2.196 USB_OTG_DN CPU.USB_OTG_DN B6
J2.198 USB_OTG_DP CPU.USB_OTG_DP A6
J2.200 USB_HOST_DP CPU.USB_HOST_DP E10
J2.202 USB_HOST_DN CPU.USB_HOST_DN F10
J2.204 DGND DGND


(*) N.B: those pins are 1V8 tolerant (i.e. must be connected to a 1V8 power domain)